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portexpander
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portexpander/platinedehaute.kicad_pcb

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changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(kicad_pcb (version 20171130) (host pcbnew 5.0.0)
start pcb layout
2018-08-26 19:54:32 +00:00
(general
(thickness 1.6)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(drawings 5)
(tracks 434)
start pcb layout
2018-08-26 19:54:32 +00:00
(zones 0)
(modules 92)
(nets 113)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user hide)
(35 F.Paste user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
(36 B.SilkS user)
(37 F.SilkS user)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(38 B.Mask user hide)
(39 F.Mask user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
(40 Dwgs.User user)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(41 Cmts.User user hide)
(42 Eco1.User user hide)
(43 Eco2.User user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
(44 Edge.Cuts user)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(45 Margin user hide)
(46 B.CrtYd user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
(47 F.CrtYd user)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(48 B.Fab user hide)
(49 F.Fab user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
)
(setup
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(last_trace_width 0.35)
(trace_clearance 0.15)
start pcb layout
2018-08-26 19:54:32 +00:00
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
add ground and power planes
2018-08-28 21:14:49 +00:00
(edge_width 0.2)
start pcb layout
2018-08-26 19:54:32 +00:00
(via_size 0.8)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(via_drill 0.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 +3V3)
(net 2 GND)
(net 3 GNDPWR)
(net 4 +24V)
(net 5 "Net-(D1-Pad1)")
(net 6 "Net-(D1-Pad2)")
(net 7 "Net-(D2-Pad2)")
(net 8 "Net-(D2-Pad1)")
(net 9 "Net-(D3-Pad1)")
(net 10 "Net-(D3-Pad2)")
(net 11 "Net-(D4-Pad2)")
(net 12 "Net-(D4-Pad1)")
(net 13 "Net-(D5-Pad2)")
(net 14 "Net-(D5-Pad1)")
(net 15 "Net-(D6-Pad1)")
(net 16 "Net-(D6-Pad2)")
(net 17 "Net-(D7-Pad2)")
(net 18 "Net-(D7-Pad1)")
(net 19 "Net-(D8-Pad1)")
(net 20 "Net-(D8-Pad2)")
(net 21 "Net-(D9-Pad1)")
(net 22 "Net-(D9-Pad2)")
(net 23 "Net-(D10-Pad2)")
(net 24 "Net-(D10-Pad1)")
(net 25 "Net-(D11-Pad1)")
(net 26 "Net-(D11-Pad2)")
(net 27 "Net-(D12-Pad2)")
(net 28 "Net-(D12-Pad1)")
(net 29 "Net-(J1-Pad2)")
(net 30 "Net-(J2-Pad2)")
(net 31 "Net-(J3-Pad2)")
(net 32 "Net-(J4-Pad1)")
(net 33 "Net-(J4-Pad2)")
(net 34 "Net-(J4-Pad3)")
(net 35 "Net-(J4-Pad6)")
(net 36 "Net-(J4-Pad7)")
(net 37 "Net-(J4-Pad8)")
(net 38 "Net-(J5-Pad8)")
(net 39 "Net-(J5-Pad7)")
(net 40 "Net-(J5-Pad6)")
(net 41 "Net-(J5-Pad3)")
(net 42 "Net-(J5-Pad2)")
(net 43 "Net-(J5-Pad1)")
(net 44 MCP_CS)
(net 45 "Net-(J6-Pad2)")
(net 46 "Net-(J6-Pad4)")
(net 47 "Net-(J6-Pad6)")
(net 48 "Net-(J6-Pad8)")
(net 49 "Net-(J6-Pad10)")
(net 50 "Net-(J6-Pad12)")
(net 51 "Net-(J6-Pad14)")
(net 52 "Net-(J6-Pad16)")
(net 53 "Net-(Q1-Pad3)")
(net 54 "Net-(Q2-Pad3)")
(net 55 "Net-(Q3-Pad3)")
(net 56 "Net-(Q4-Pad3)")
(net 57 "Net-(Q5-Pad3)")
(net 58 "Net-(Q6-Pad3)")
(net 59 "Net-(Q7-Pad3)")
(net 60 "Net-(Q8-Pad3)")
(net 61 "Net-(Q9-Pad3)")
(net 62 "Net-(Q10-Pad3)")
(net 63 "Net-(Q11-Pad3)")
(net 64 "Net-(Q12-Pad3)")
(net 65 +5V)
(net 66 "Net-(R1-Pad2)")
(net 67 "Net-(R17-Pad1)")
(net 68 "Net-(R19-Pad1)")
(net 69 "Net-(R21-Pad1)")
(net 70 "Net-(R23-Pad1)")
(net 71 "Net-(R25-Pad1)")
(net 72 "Net-(R27-Pad1)")
(net 73 "Net-(R29-Pad1)")
(net 74 "Net-(R31-Pad1)")
(net 75 "Net-(R33-Pad1)")
(net 76 "Net-(R35-Pad1)")
(net 77 "Net-(R36-Pad1)")
(net 78 "Net-(R37-Pad1)")
(net 79 "Net-(TP1-Pad1)")
(net 80 "Net-(TP2-Pad1)")
(net 81 "Net-(TP3-Pad1)")
(net 82 "Net-(TP4-Pad1)")
(net 83 "Net-(TP5-Pad1)")
(net 84 "Net-(TP6-Pad1)")
(net 85 "Net-(TP7-Pad1)")
(net 86 "Net-(TP8-Pad1)")
(net 87 "Net-(TP9-Pad1)")
(net 88 "Net-(TP10-Pad1)")
(net 89 "Net-(TP11-Pad1)")
(net 90 "Net-(TP12-Pad1)")
(net 91 "Net-(TP13-Pad1)")
(net 92 "Net-(TP14-Pad1)")
(net 93 "Net-(TP15-Pad1)")
(net 94 "Net-(TP16-Pad1)")
(net 95 SCK)
(net 96 MOSI)
(net 97 MISO)
(net 98 "Net-(U1-Pad19)")
(net 99 "Net-(U1-Pad20)")
(net 100 "Net-(J7-Pad27)")
(net 101 "Net-(J7-Pad26)")
(net 102 "Net-(J7-Pad25)")
(net 103 "Net-(J7-Pad24)")
(net 104 "Net-(J7-Pad23)")
(net 105 "Net-(J7-Pad22)")
(net 106 "Net-(J7-Pad21)")
(net 107 "Net-(J7-Pad20)")
(net 108 "Net-(J7-Pad19)")
(net 109 "Net-(J7-Pad18)")
(net 110 "Net-(J7-Pad17)")
(net 111 "Net-(J7-Pad16)")
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 112 +12V)
start pcb layout
2018-08-26 19:54:32 +00:00
(net_class Default "This is the default net class."
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(clearance 0.15)
(trace_width 0.35)
start pcb layout
2018-08-26 19:54:32 +00:00
(via_dia 0.8)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(via_drill 0.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(uvia_dia 0.3)
(uvia_drill 0.1)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(add_net +12V)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(add_net +24V)
start pcb layout
2018-08-26 19:54:32 +00:00
(add_net +5V)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(add_net GNDPWR)
start pcb layout
2018-08-26 19:54:32 +00:00
(add_net MCP_CS)
(add_net MISO)
(add_net MOSI)
(add_net "Net-(D1-Pad1)")
(add_net "Net-(D1-Pad2)")
(add_net "Net-(D10-Pad1)")
(add_net "Net-(D10-Pad2)")
(add_net "Net-(D11-Pad1)")
(add_net "Net-(D11-Pad2)")
(add_net "Net-(D12-Pad1)")
(add_net "Net-(D12-Pad2)")
(add_net "Net-(D2-Pad1)")
(add_net "Net-(D2-Pad2)")
(add_net "Net-(D3-Pad1)")
(add_net "Net-(D3-Pad2)")
(add_net "Net-(D4-Pad1)")
(add_net "Net-(D4-Pad2)")
(add_net "Net-(D5-Pad1)")
(add_net "Net-(D5-Pad2)")
(add_net "Net-(D6-Pad1)")
(add_net "Net-(D6-Pad2)")
(add_net "Net-(D7-Pad1)")
(add_net "Net-(D7-Pad2)")
(add_net "Net-(D8-Pad1)")
(add_net "Net-(D8-Pad2)")
(add_net "Net-(D9-Pad1)")
(add_net "Net-(D9-Pad2)")
(add_net "Net-(J1-Pad2)")
(add_net "Net-(J2-Pad2)")
(add_net "Net-(J3-Pad2)")
(add_net "Net-(J4-Pad1)")
(add_net "Net-(J4-Pad2)")
(add_net "Net-(J4-Pad3)")
(add_net "Net-(J4-Pad6)")
(add_net "Net-(J4-Pad7)")
(add_net "Net-(J4-Pad8)")
(add_net "Net-(J5-Pad1)")
(add_net "Net-(J5-Pad2)")
(add_net "Net-(J5-Pad3)")
(add_net "Net-(J5-Pad6)")
(add_net "Net-(J5-Pad7)")
(add_net "Net-(J5-Pad8)")
(add_net "Net-(J6-Pad10)")
(add_net "Net-(J6-Pad12)")
(add_net "Net-(J6-Pad14)")
(add_net "Net-(J6-Pad16)")
(add_net "Net-(J6-Pad2)")
(add_net "Net-(J6-Pad4)")
(add_net "Net-(J6-Pad6)")
(add_net "Net-(J6-Pad8)")
(add_net "Net-(J7-Pad16)")
(add_net "Net-(J7-Pad17)")
(add_net "Net-(J7-Pad18)")
(add_net "Net-(J7-Pad19)")
(add_net "Net-(J7-Pad20)")
(add_net "Net-(J7-Pad21)")
(add_net "Net-(J7-Pad22)")
(add_net "Net-(J7-Pad23)")
(add_net "Net-(J7-Pad24)")
(add_net "Net-(J7-Pad25)")
(add_net "Net-(J7-Pad26)")
(add_net "Net-(J7-Pad27)")
(add_net "Net-(Q1-Pad3)")
(add_net "Net-(Q10-Pad3)")
(add_net "Net-(Q11-Pad3)")
(add_net "Net-(Q12-Pad3)")
(add_net "Net-(Q2-Pad3)")
(add_net "Net-(Q3-Pad3)")
(add_net "Net-(Q4-Pad3)")
(add_net "Net-(Q5-Pad3)")
(add_net "Net-(Q6-Pad3)")
(add_net "Net-(Q7-Pad3)")
(add_net "Net-(Q8-Pad3)")
(add_net "Net-(Q9-Pad3)")
(add_net "Net-(R1-Pad2)")
(add_net "Net-(R17-Pad1)")
(add_net "Net-(R19-Pad1)")
(add_net "Net-(R21-Pad1)")
(add_net "Net-(R23-Pad1)")
(add_net "Net-(R25-Pad1)")
(add_net "Net-(R27-Pad1)")
(add_net "Net-(R29-Pad1)")
(add_net "Net-(R31-Pad1)")
(add_net "Net-(R33-Pad1)")
(add_net "Net-(R35-Pad1)")
(add_net "Net-(R36-Pad1)")
(add_net "Net-(R37-Pad1)")
(add_net "Net-(TP1-Pad1)")
(add_net "Net-(TP10-Pad1)")
(add_net "Net-(TP11-Pad1)")
(add_net "Net-(TP12-Pad1)")
(add_net "Net-(TP13-Pad1)")
(add_net "Net-(TP14-Pad1)")
(add_net "Net-(TP15-Pad1)")
(add_net "Net-(TP16-Pad1)")
(add_net "Net-(TP2-Pad1)")
(add_net "Net-(TP3-Pad1)")
(add_net "Net-(TP4-Pad1)")
(add_net "Net-(TP5-Pad1)")
(add_net "Net-(TP6-Pad1)")
(add_net "Net-(TP7-Pad1)")
(add_net "Net-(TP8-Pad1)")
(add_net "Net-(TP9-Pad1)")
(add_net "Net-(U1-Pad19)")
(add_net "Net-(U1-Pad20)")
(add_net SCK)
)
add ground and power planes
2018-08-28 21:14:49 +00:00
(net_class "Power 3v3" ""
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(clearance 0.15)
add ground and power planes
2018-08-28 21:14:49 +00:00
(trace_width 0.5)
(via_dia 0.8)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(via_drill 0.5)
add ground and power planes
2018-08-28 21:14:49 +00:00
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +3V3)
(add_net GND)
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(module Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm (layer F.Cu) (tedit 5A02F2D3) (tstamp 5BA679D4)
(at 182.88 93.98 90)
(descr "28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5B9C3DF9)
(attr smd)
(fp_text reference U1 (at 0 -10.05 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MCP23S17 (at 0 10.05 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.75 -8.95) (end 3.75 -8.95) (layer F.Fab) (width 0.15))
(fp_line (start 3.75 -8.95) (end 3.75 8.95) (layer F.Fab) (width 0.15))
(fp_line (start 3.75 8.95) (end -3.75 8.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.75 8.95) (end -3.75 -7.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.75 -7.95) (end -2.75 -8.95) (layer F.Fab) (width 0.15))
(fp_line (start -5.95 -9.3) (end -5.95 9.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.95 -9.3) (end 5.95 9.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 -9.3) (end 5.95 -9.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 9.3) (end 5.95 9.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.875 -9.125) (end -3.875 -8.875) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 -9.125) (end 3.875 -8.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 9.125) (end 3.875 8.78) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 9.125) (end -3.875 8.78) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -9.125) (end 3.875 -9.125) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 9.125) (end 3.875 9.125) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -8.875) (end -5.7 -8.875) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -4.7 -8.255 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 94 "Net-(TP16-Pad1)"))
(pad 2 smd rect (at -4.7 -6.985 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 88 "Net-(TP10-Pad1)"))
(pad 3 smd rect (at -4.7 -5.715 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 89 "Net-(TP11-Pad1)"))
(pad 4 smd rect (at -4.7 -4.445 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 90 "Net-(TP12-Pad1)"))
(pad 5 smd rect (at -4.7 -3.175 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 91 "Net-(TP13-Pad1)"))
(pad 6 smd rect (at -4.7 -1.905 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 92 "Net-(TP14-Pad1)"))
(pad 7 smd rect (at -4.7 -0.635 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 93 "Net-(TP15-Pad1)"))
(pad 8 smd rect (at -4.7 0.635 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 87 "Net-(TP9-Pad1)"))
(pad 9 smd rect (at -4.7 1.905 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 1 +3V3))
(pad 10 smd rect (at -4.7 3.175 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 11 smd rect (at -4.7 4.445 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 12 smd rect (at -4.7 5.715 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 95 SCK))
(pad 13 smd rect (at -4.7 6.985 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 96 MOSI))
(pad 14 smd rect (at -4.7 8.255 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 97 MISO))
(pad 15 smd rect (at 4.7 8.255 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 "Net-(J3-Pad2)"))
(pad 16 smd rect (at 4.7 6.985 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 30 "Net-(J2-Pad2)"))
(pad 17 smd rect (at 4.7 5.715 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 29 "Net-(J1-Pad2)"))
(pad 18 smd rect (at 4.7 4.445 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 66 "Net-(R1-Pad2)"))
(pad 19 smd rect (at 4.7 3.175 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 98 "Net-(U1-Pad19)"))
(pad 20 smd rect (at 4.7 1.905 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 99 "Net-(U1-Pad20)"))
(pad 21 smd rect (at 4.7 0.635 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 85 "Net-(TP7-Pad1)"))
(pad 22 smd rect (at 4.7 -0.635 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 86 "Net-(TP8-Pad1)"))
(pad 23 smd rect (at 4.7 -1.905 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 84 "Net-(TP6-Pad1)"))
(pad 24 smd rect (at 4.7 -3.175 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 83 "Net-(TP5-Pad1)"))
(pad 25 smd rect (at 4.7 -4.445 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 79 "Net-(TP1-Pad1)"))
(pad 26 smd rect (at 4.7 -5.715 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 80 "Net-(TP2-Pad1)"))
(pad 27 smd rect (at 4.7 -6.985 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 81 "Net-(TP3-Pad1)"))
(pad 28 smd rect (at 4.7 -8.255 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 82 "Net-(TP4-Pad1)"))
(model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-28W_7.5x17.9mm_P1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(module DIN41617:DIN41617_31_short (layer F.Cu) (tedit 5B85C041) (tstamp 5BA674A6)
(at 221.75 89.49 90)
(path /5C0C9A4A)
(fp_text reference J7 (at -43.25 -6 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x31 (at 40 -5.75 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 35 -1.25) (end 35 7.637659) (layer F.SilkS) (width 1))
(fp_line (start 30 -1.25) (end 30 7.632978) (layer F.SilkS) (width 1))
(fp_line (start 25 -1.25) (end 25 7.623112) (layer F.SilkS) (width 1))
(fp_line (start 20 -1.25) (end 20 7.670728) (layer F.SilkS) (width 1))
(fp_line (start 15 -1.25) (end 15 7.62879) (layer F.SilkS) (width 1))
(fp_line (start 10 -1.25) (end 10 7.655555) (layer F.SilkS) (width 1))
(fp_line (start 5 -1.25) (end 5 7.64877) (layer F.SilkS) (width 1))
(fp_line (start 0 -1.25) (end 0 7.62) (layer F.SilkS) (width 1))
(fp_line (start -5 -1.25) (end -5 7.64877) (layer F.SilkS) (width 1))
(fp_line (start -10 -1.25) (end -10 7.632709) (layer F.SilkS) (width 1))
(fp_line (start -15 -1.25) (end -15 7.623246) (layer F.SilkS) (width 1))
(fp_line (start -20 -1.25) (end -20 7.625591) (layer F.SilkS) (width 1))
(fp_line (start -25 -1.25) (end -25 7.623112) (layer F.SilkS) (width 1))
(fp_line (start -30 -1.25) (end -30 7.632978) (layer F.SilkS) (width 1))
(fp_line (start -35 -1.25) (end -35 7.620317) (layer F.SilkS) (width 1))
(fp_line (start -32.5 1.25) (end -32.5 7.664) (layer F.SilkS) (width 1))
(fp_line (start -22.5 1.25) (end -22.5 7.625933) (layer F.SilkS) (width 1))
(fp_line (start -12.5 1.25) (end -12.5 7.623138) (layer F.SilkS) (width 1))
(fp_line (start -2.5 1.25) (end -2.5 7.647728) (layer F.SilkS) (width 1))
(fp_line (start 7.5 1.25) (end 7.5 7.62113) (layer F.SilkS) (width 1))
(fp_line (start 17.5 1.25) (end 17.5 7.62615) (layer F.SilkS) (width 1))
(fp_line (start 27.5 1.25) (end 27.5 7.635178) (layer F.SilkS) (width 1))
(fp_line (start 37.5 1.25) (end 37.5 7.648195) (layer F.SilkS) (width 1))
(fp_line (start 32.5 1.25) (end 32.5 7.621037) (layer F.SilkS) (width 1))
(fp_line (start 22.5 1.25) (end 22.5 7.625933) (layer F.SilkS) (width 1))
(fp_line (start 12.5 1.25) (end 12.5 7.634835) (layer F.SilkS) (width 1))
(fp_line (start 2.5 1.25) (end 2.5 7.620125) (layer F.SilkS) (width 1))
(fp_line (start -7.5 1.25) (end -7.5 7.640784) (layer F.SilkS) (width 1))
(fp_line (start -17.5 1.25) (end -17.5 7.62615) (layer F.SilkS) (width 1))
(fp_line (start -27.5 1.25) (end -27.5 7.622983) (layer F.SilkS) (width 1))
(fp_line (start -37.5 1.25) (end -37.465 7.62) (layer F.SilkS) (width 1))
(fp_line (start -45.3 -4.75) (end -45.3 8.25) (layer F.CrtYd) (width 0.15))
(fp_line (start 45.3 -4.75) (end -45.3 -4.75) (layer F.CrtYd) (width 0.15))
(fp_line (start 45.3 8.25) (end 45.3 -4.75) (layer F.CrtYd) (width 0.15))
(fp_line (start -45.3 8.25) (end 45.3 8.25) (layer F.CrtYd) (width 0.15))
(pad "" np_thru_hole circle (at 42.5 3.75 90) (size 3 3) (drill 3) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -42.5 3.75 90) (size 3 3) (drill 3) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 37.5 1.25 90) (size 2.2 2.2) (drill 1.31) (layers *.Cu *.Mask)
(net 2 GND))
(pad 2 thru_hole circle (at 35 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 112 +12V))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 3 thru_hole circle (at 32.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 65 +5V))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 4 thru_hole circle (at 30 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 1 +3V3))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 5 thru_hole circle (at 27.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 45 "Net-(J6-Pad2)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 6 thru_hole circle (at 25 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 46 "Net-(J6-Pad4)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 7 thru_hole circle (at 22.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 47 "Net-(J6-Pad6)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 8 thru_hole circle (at 20 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 48 "Net-(J6-Pad8)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 9 thru_hole circle (at 17.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 49 "Net-(J6-Pad10)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 10 thru_hole circle (at 15 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 50 "Net-(J6-Pad12)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 11 thru_hole circle (at 12.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 51 "Net-(J6-Pad14)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 12 thru_hole circle (at 10 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 52 "Net-(J6-Pad16)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 13 thru_hole circle (at 7.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 95 SCK))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 14 thru_hole circle (at 5 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 96 MOSI))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 15 thru_hole circle (at 2.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 97 MISO))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 16 thru_hole circle (at 0 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 111 "Net-(J7-Pad16)"))
(pad 17 thru_hole circle (at -2.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 110 "Net-(J7-Pad17)"))
(pad 18 thru_hole circle (at -5 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 109 "Net-(J7-Pad18)"))
(pad 19 thru_hole circle (at -7.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 108 "Net-(J7-Pad19)"))
(pad 20 thru_hole circle (at -10 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 107 "Net-(J7-Pad20)"))
(pad 21 thru_hole circle (at -12.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 106 "Net-(J7-Pad21)"))
(pad 22 thru_hole circle (at -15 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 105 "Net-(J7-Pad22)"))
(pad 23 thru_hole circle (at -17.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 104 "Net-(J7-Pad23)"))
(pad 24 thru_hole circle (at -20 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 103 "Net-(J7-Pad24)"))
(pad 25 thru_hole circle (at -22.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 102 "Net-(J7-Pad25)"))
(pad 26 thru_hole circle (at -25 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 101 "Net-(J7-Pad26)"))
(pad 27 thru_hole circle (at -27.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 100 "Net-(J7-Pad27)"))
(pad 28 thru_hole circle (at -30 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 29 thru_hole circle (at -32.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 30 thru_hole circle (at -35 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 31 thru_hole circle (at -37.5 1.25 90) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask)
(net 3 GNDPWR))
)
start pcb layout
2018-08-26 19:54:32 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA675EF)
route more pcb
2018-08-26 20:13:25 +00:00
(at 187.325 85.09 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BFDF8F4)
(attr smd)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference R1 (at 0 -1.43 270) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value 10k (at 0 1.43 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 smd roundrect (at -0.7875 0 270) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
route some more
2018-08-26 20:30:55 +00:00
(net 1 +3V3))
route more pcb
2018-08-26 20:13:25 +00:00
(pad 2 smd roundrect (at 0.7875 0 270) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 66 "Net-(R1-Pad2)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5BA67212)
route more pcb
2018-08-26 20:13:25 +00:00
(at 185.42 101.6)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags capacitor)
(path /5CA079CD)
(attr smd)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference C1 (at 0 -1.43) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value 100nF (at 0 1.43) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 1 +3V3))
route more pcb
2018-08-26 20:13:25 +00:00
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 2 GND))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_SMD:CP_Elec_6.3x5.2 (layer F.Cu) (tedit 5B3026A2) (tstamp 5BA6723A)
route some more
2018-08-26 20:30:55 +00:00
(at 207.645 50.8 90)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "SMT capacitor, aluminium electrolytic, 6.3x5.2, United Chemi-Con ")
(tags "Capacitor Electrolytic")
(path /5CA07BF6)
(attr smd)
(fp_text reference C2 (at 0 -4.35 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100µF (at 0 4.35 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.15 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.3 -3.3) (end 3.3 3.3) (layer F.Fab) (width 0.1))
(fp_line (start -2.3 -3.3) (end 3.3 -3.3) (layer F.Fab) (width 0.1))
(fp_line (start -2.3 3.3) (end 3.3 3.3) (layer F.Fab) (width 0.1))
(fp_line (start -3.3 -2.3) (end -3.3 2.3) (layer F.Fab) (width 0.1))
(fp_line (start -3.3 -2.3) (end -2.3 -3.3) (layer F.Fab) (width 0.1))
(fp_line (start -3.3 2.3) (end -2.3 3.3) (layer F.Fab) (width 0.1))
(fp_line (start -2.704838 -1.33) (end -2.074838 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -2.389838 -1.645) (end -2.389838 -1.015) (layer F.Fab) (width 0.1))
(fp_line (start 3.41 3.41) (end 3.41 1.06) (layer F.SilkS) (width 0.12))
(fp_line (start 3.41 -3.41) (end 3.41 -1.06) (layer F.SilkS) (width 0.12))
(fp_line (start -2.345563 -3.41) (end 3.41 -3.41) (layer F.SilkS) (width 0.12))
(fp_line (start -2.345563 3.41) (end 3.41 3.41) (layer F.SilkS) (width 0.12))
(fp_line (start -3.41 2.345563) (end -3.41 1.06) (layer F.SilkS) (width 0.12))
(fp_line (start -3.41 -2.345563) (end -3.41 -1.06) (layer F.SilkS) (width 0.12))
(fp_line (start -3.41 -2.345563) (end -2.345563 -3.41) (layer F.SilkS) (width 0.12))
(fp_line (start -3.41 2.345563) (end -2.345563 3.41) (layer F.SilkS) (width 0.12))
(fp_line (start -4.4375 -1.8475) (end -3.65 -1.8475) (layer F.SilkS) (width 0.12))
(fp_line (start -4.04375 -2.24125) (end -4.04375 -1.45375) (layer F.SilkS) (width 0.12))
(fp_line (start 3.55 -3.55) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.05) (end 4.8 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.8 -1.05) (end 4.8 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.8 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.4 3.55) (end 3.55 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.4 -3.55) (end 3.55 -3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 2.4) (end -2.4 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 -2.4) (end -2.4 -3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 -2.4) (end -3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 1.05) (end -3.55 2.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 -1.05) (end -4.8 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.8 -1.05) (end -4.8 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.8 1.05) (end -3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at -2.8 0 90) (size 3.5 1.6) (layers F.Cu F.Paste F.Mask)
(net 1 +3V3))
(pad 2 smd rect (at 2.8 0 90) (size 3.5 1.6) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/CP_Elec_6.3x5.2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5BA6724B)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 128.905 101.6 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags capacitor)
(path /5C0C7E69)
(attr smd)
add ground and power planes
2018-08-28 21:14:49 +00:00
(fp_text reference C3 (at 0 -1.43 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
add ground and power planes
2018-08-28 21:14:49 +00:00
(fp_text value 100nF (at 0 1.43 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
add ground and power planes
2018-08-28 21:14:49 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
add ground and power planes
2018-08-28 21:14:49 +00:00
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 3 GNDPWR))
add ground and power planes
2018-08-28 21:14:49 +00:00
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 4 +24V))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitor_SMD:CP_Elec_10x10 (layer F.Cu) (tedit 5A841F9D) (tstamp 5BA67273)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 83.82 90.17 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "SMT capacitor, aluminium electrolytic, 10x10, Nichicon ")
(tags "Capacitor Electrolytic")
(path /5C0C76F7)
(attr smd)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(fp_text reference C4 (at 0 -6.2 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(fp_text value 100µF (at 0 6.2 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 5 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.15 -5.15) (end 5.15 5.15) (layer F.Fab) (width 0.1))
(fp_line (start -4.15 -5.15) (end 5.15 -5.15) (layer F.Fab) (width 0.1))
(fp_line (start -4.15 5.15) (end 5.15 5.15) (layer F.Fab) (width 0.1))
(fp_line (start -5.15 -4.15) (end -5.15 4.15) (layer F.Fab) (width 0.1))
(fp_line (start -5.15 -4.15) (end -4.15 -5.15) (layer F.Fab) (width 0.1))
(fp_line (start -5.15 4.15) (end -4.15 5.15) (layer F.Fab) (width 0.1))
(fp_line (start -4.558325 -1.7) (end -3.558325 -1.7) (layer F.Fab) (width 0.1))
(fp_line (start -4.058325 -2.2) (end -4.058325 -1.2) (layer F.Fab) (width 0.1))
(fp_line (start 5.26 5.26) (end 5.26 1.51) (layer F.SilkS) (width 0.12))
(fp_line (start 5.26 -5.26) (end 5.26 -1.51) (layer F.SilkS) (width 0.12))
(fp_line (start -4.195563 -5.26) (end 5.26 -5.26) (layer F.SilkS) (width 0.12))
(fp_line (start -4.195563 5.26) (end 5.26 5.26) (layer F.SilkS) (width 0.12))
(fp_line (start -5.26 4.195563) (end -5.26 1.51) (layer F.SilkS) (width 0.12))
(fp_line (start -5.26 -4.195563) (end -5.26 -1.51) (layer F.SilkS) (width 0.12))
(fp_line (start -5.26 -4.195563) (end -4.195563 -5.26) (layer F.SilkS) (width 0.12))
(fp_line (start -5.26 4.195563) (end -4.195563 5.26) (layer F.SilkS) (width 0.12))
(fp_line (start -6.75 -2.76) (end -5.5 -2.76) (layer F.SilkS) (width 0.12))
(fp_line (start -6.125 -3.385) (end -6.125 -2.135) (layer F.SilkS) (width 0.12))
(fp_line (start 5.4 -5.4) (end 5.4 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.4 -1.5) (end 6.25 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.25 -1.5) (end 6.25 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.25 1.5) (end 5.4 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.4 1.5) (end 5.4 5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.25 5.4) (end 5.4 5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.25 -5.4) (end 5.4 -5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 4.25) (end -4.25 5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 -4.25) (end -4.25 -5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 -4.25) (end -5.4 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 1.5) (end -5.4 4.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 -1.5) (end -6.25 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.25 -1.5) (end -6.25 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.25 1.5) (end -5.4 1.5) (layer F.CrtYd) (width 0.05))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 1 smd rect (at -4 0 180) (size 4 2.5) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 4 +24V))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 2 smd rect (at 4 0 180) (size 4 2.5) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/CP_Elec_10x10.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA67286)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 125.73 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B98D69F)
(attr smd)
(fp_text reference D1 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 5 "Net-(D1-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 6 "Net-(D1-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA67299)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 120.65 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B98D6A5)
(attr smd)
(fp_text reference D2 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 7 "Net-(D2-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 8 "Net-(D2-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA672AC)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 115.57 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B98D6AB)
(attr smd)
(fp_text reference D3 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 9 "Net-(D3-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 10 "Net-(D3-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA672BF)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 110.49 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B98D6B1)
(attr smd)
(fp_text reference D4 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 11 "Net-(D4-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 12 "Net-(D4-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA672D2)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 93.98 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9871BF)
(attr smd)
(fp_text reference D5 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 13 "Net-(D5-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 14 "Net-(D5-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA672E5)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.727498 88.9 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B987245)
(attr smd)
(fp_text reference D6 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 15 "Net-(D6-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 16 "Net-(D6-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA672F8)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 83.82 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9872A3)
(attr smd)
(fp_text reference D7 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 17 "Net-(D7-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 18 "Net-(D7-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA6730B)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B987307)
(attr smd)
(fp_text reference D8 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 19 "Net-(D8-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 20 "Net-(D8-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA6731E)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 60.96 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9937BB)
(attr smd)
(fp_text reference D9 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 21 "Net-(D9-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 22 "Net-(D9-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA67331)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 55.88 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9937C1)
(attr smd)
(fp_text reference D10 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 23 "Net-(D10-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 24 "Net-(D10-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA67344)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 50.8 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9937C7)
(attr smd)
(fp_text reference D11 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 25 "Net-(D11-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 26 "Net-(D11-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BA67357)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 45.72 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9937CD)
(attr smd)
(fp_text reference D12 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 27 "Net-(D12-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 28 "Net-(D12-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA67379)
route some more
2018-08-26 20:30:55 +00:00
(at 179.705 45.085 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left)")
(tags "Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left")
(path /5C938F53)
(attr smd)
route some more
2018-08-26 20:30:55 +00:00
(fp_text reference J1 (at 0 -4.87 270) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(fp_text value ADDR2 (at 0 4.87 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -3.81) (end 1.27 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -0.32 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -3.81) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -2.54 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.86) (end -2.54 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.22) (end -1.27 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 2.22) (end -2.54 2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.22) (end -2.54 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.86) (end -1.27 2.86) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.32) (end 2.54 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -0.32) (end 2.54 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 0.32) (end 1.27 0.32) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 -3.87) (end 1.33 -3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.87) (end 1.33 -0.76) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.3) (end -2.85 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.87) (end -1.33 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 3.3) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 0.76) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.78) (end -1.33 1.78) (layer F.SilkS) (width 0.12))
(fp_line (start -3.45 -4.35) (end -3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.45 4.35) (end 3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 4.35) (end 3.45 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 -4.35) (end -3.45 -4.35) (layer F.CrtYd) (width 0.05))
route some more
2018-08-26 20:30:55 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(pad 1 smd rect (at -1.655 -2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 1 +3V3))
route some more
2018-08-26 20:30:55 +00:00
(pad 3 smd rect (at -1.655 2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 2 GND))
route some more
2018-08-26 20:30:55 +00:00
(pad 2 smd rect (at 1.655 0 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 29 "Net-(J1-Pad2)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA6739B)
route some more
2018-08-26 20:30:55 +00:00
(at 188.595 45.085 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left)")
(tags "Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left")
(path /5C93924C)
(attr smd)
route some more
2018-08-26 20:30:55 +00:00
(fp_text reference J2 (at 0 -4.87 270) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(fp_text value ADDR1 (at 0 4.87 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.45 -4.35) (end -3.45 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 4.35) (end 3.45 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.45 4.35) (end 3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.45 -4.35) (end -3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.78) (end -1.33 1.78) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 0.76) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 3.3) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.87) (end -1.33 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.3) (end -2.85 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.87) (end 1.33 -0.76) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.87) (end 1.33 -3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 0.32) (end 1.27 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -0.32) (end 2.54 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.32) (end 2.54 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.86) (end -1.27 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.22) (end -2.54 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 2.22) (end -2.54 2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.22) (end -1.27 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.86) (end -2.54 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -2.54 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -3.81) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -0.32 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -3.81) (end 1.27 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
route some more
2018-08-26 20:30:55 +00:00
(pad 2 smd rect (at 1.655 0 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 30 "Net-(J2-Pad2)"))
route some more
2018-08-26 20:30:55 +00:00
(pad 3 smd rect (at -1.655 2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 2 GND))
route some more
2018-08-26 20:30:55 +00:00
(pad 1 smd rect (at -1.655 -2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 1 +3V3))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA673BD)
route some more
2018-08-26 20:30:55 +00:00
(at 197.485 45.085 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left)")
(tags "Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left")
(path /5C9392FE)
(attr smd)
route some more
2018-08-26 20:30:55 +00:00
(fp_text reference J3 (at 0 -4.87 270) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(fp_text value ADDR0 (at 0 4.87 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -3.81) (end 1.27 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -0.32 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -3.81) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -2.54 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.86) (end -2.54 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.22) (end -1.27 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 2.22) (end -2.54 2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.22) (end -2.54 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.86) (end -1.27 2.86) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.32) (end 2.54 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -0.32) (end 2.54 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 0.32) (end 1.27 0.32) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 -3.87) (end 1.33 -3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.87) (end 1.33 -0.76) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.3) (end -2.85 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.87) (end -1.33 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 3.3) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 0.76) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.78) (end -1.33 1.78) (layer F.SilkS) (width 0.12))
(fp_line (start -3.45 -4.35) (end -3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.45 4.35) (end 3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 4.35) (end 3.45 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 -4.35) (end -3.45 -4.35) (layer F.CrtYd) (width 0.05))
route some more
2018-08-26 20:30:55 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(pad 1 smd rect (at -1.655 -2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 1 +3V3))
route some more
2018-08-26 20:30:55 +00:00
(pad 3 smd rect (at -1.655 2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 2 GND))
route some more
2018-08-26 20:30:55 +00:00
(pad 2 smd rect (at 1.655 0 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 31 "Net-(J3-Pad2)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_RJ:RJ45_Amphenol_54602-x08_Horizontal (layer F.Cu) (tedit 5B103613) (tstamp 5BA673DC)
(at 83.82 102.87 270)
(descr "8 Pol Shallow Latch Connector, Modjack, RJ45 (https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0102.pdf)")
(tags RJ45)
(path /5B72E546)
(fp_text reference J4 (at 4.445 -5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 8P8C (at 4.445 4 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.445 2 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -4 0.5) (end -3.5 0) (layer F.SilkS) (width 0.12))
(fp_line (start -4 -0.5) (end -4 0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -3.5 0) (end -4 -0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -3.205 13.97) (end -3.205 -2.77) (layer F.Fab) (width 0.12))
(fp_line (start 12.095 13.97) (end -3.205 13.97) (layer F.Fab) (width 0.12))
(fp_line (start 12.095 -3.77) (end 12.095 13.97) (layer F.Fab) (width 0.12))
(fp_line (start -2.205 -3.77) (end 12.095 -3.77) (layer F.Fab) (width 0.12))
(fp_line (start -3.205 -2.77) (end -2.205 -3.77) (layer F.Fab) (width 0.12))
(fp_line (start -3.315 14.08) (end 12.205 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start 12.205 -3.88) (end 12.205 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start 12.205 -3.88) (end -3.315 -3.88) (layer F.SilkS) (width 0.12))
(fp_line (start -3.315 -3.88) (end -3.315 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start -3.71 -4.27) (end 12.6 -4.27) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.71 -4.27) (end -3.71 14.47) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 14.47) (end 12.6 -4.27) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 14.47) (end -3.71 14.47) (layer F.CrtYd) (width 0.05))
(pad "" np_thru_hole circle (at 10.16 6.35 270) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -1.27 6.35 270) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 0 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 32 "Net-(J4-Pad1)"))
(pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 33 "Net-(J4-Pad2)"))
(pad 3 thru_hole circle (at 2.54 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 34 "Net-(J4-Pad3)"))
(pad 4 thru_hole circle (at 3.81 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 5 thru_hole circle (at 5.08 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 6 thru_hole circle (at 6.35 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 35 "Net-(J4-Pad6)"))
(pad 7 thru_hole circle (at 7.62 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 36 "Net-(J4-Pad7)"))
(pad 8 thru_hole circle (at 8.89 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 37 "Net-(J4-Pad8)"))
(model ${KISYS3DMOD}/Connector_RJ.3dshapes/RJ45_Amphenol_54602-x08_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_RJ:RJ45_Amphenol_54602-x08_Horizontal (layer F.Cu) (tedit 5B103613) (tstamp 5BA673FB)
route some more
2018-08-26 20:30:55 +00:00
(at 83.82 68.58 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "8 Pol Shallow Latch Connector, Modjack, RJ45 (https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0102.pdf)")
(tags RJ45)
(path /5B742CE5)
(fp_text reference J5 (at 4.445 -5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 8P8C (at 4.445 4 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 12.6 14.47) (end -3.71 14.47) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 14.47) (end 12.6 -4.27) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.71 -4.27) (end -3.71 14.47) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.71 -4.27) (end 12.6 -4.27) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.315 -3.88) (end -3.315 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start 12.205 -3.88) (end -3.315 -3.88) (layer F.SilkS) (width 0.12))
(fp_line (start 12.205 -3.88) (end 12.205 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start -3.315 14.08) (end 12.205 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start -3.205 -2.77) (end -2.205 -3.77) (layer F.Fab) (width 0.12))
(fp_line (start -2.205 -3.77) (end 12.095 -3.77) (layer F.Fab) (width 0.12))
(fp_line (start 12.095 -3.77) (end 12.095 13.97) (layer F.Fab) (width 0.12))
(fp_line (start 12.095 13.97) (end -3.205 13.97) (layer F.Fab) (width 0.12))
(fp_line (start -3.205 13.97) (end -3.205 -2.77) (layer F.Fab) (width 0.12))
(fp_line (start -3.5 0) (end -4 -0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -4 -0.5) (end -4 0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -4 0.5) (end -3.5 0) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 4.445 2 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 8 thru_hole circle (at 8.89 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 38 "Net-(J5-Pad8)"))
(pad 7 thru_hole circle (at 7.62 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 39 "Net-(J5-Pad7)"))
(pad 6 thru_hole circle (at 6.35 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 40 "Net-(J5-Pad6)"))
(pad 5 thru_hole circle (at 5.08 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 4 thru_hole circle (at 3.81 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 3 thru_hole circle (at 2.54 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 41 "Net-(J5-Pad3)"))
(pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 42 "Net-(J5-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 43 "Net-(J5-Pad1)"))
(pad "" np_thru_hole circle (at -1.27 6.35 270) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 10.16 6.35 270) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Connector_RJ.3dshapes/RJ45_Amphenol_54602-x08_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_2x08_P2.54mm_Vertical_SMD (layer F.Cu) (tedit 59FED5CC) (tstamp 5BB6B0A6)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(at 201.93 69.85)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "surface-mounted straight pin header, 2x08, 2.54mm pitch, double rows")
(tags "Surface mounted pin header SMD 2x08 2.54mm double row")
(path /5C251F2C)
(attr smd)
(fp_text reference J6 (at 0 -11.22) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_02x08_Odd_Even (at 0 11.22) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 2.54 10.16) (end -2.54 10.16) (layer F.Fab) (width 0.1))
(fp_line (start -1.59 -10.16) (end 2.54 -10.16) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 10.16) (end -2.54 -9.21) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -9.21) (end -1.59 -10.16) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -10.16) (end 2.54 10.16) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -9.21) (end -3.6 -9.21) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -9.21) (end -3.6 -8.57) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -8.57) (end -2.54 -8.57) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -9.21) (end 3.6 -9.21) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -9.21) (end 3.6 -8.57) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -8.57) (end 2.54 -8.57) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -6.67) (end -3.6 -6.67) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -6.67) (end -3.6 -6.03) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -6.03) (end -2.54 -6.03) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -6.67) (end 3.6 -6.67) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -6.67) (end 3.6 -6.03) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -6.03) (end 2.54 -6.03) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -4.13) (end -3.6 -4.13) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -4.13) (end -3.6 -3.49) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -3.49) (end -2.54 -3.49) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -4.13) (end 3.6 -4.13) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -4.13) (end 3.6 -3.49) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -3.49) (end 2.54 -3.49) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -1.59) (end -3.6 -1.59) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -1.59) (end -3.6 -0.95) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -0.95) (end -2.54 -0.95) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -1.59) (end 3.6 -1.59) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -1.59) (end 3.6 -0.95) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -0.95) (end 2.54 -0.95) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 0.95) (end -3.6 0.95) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 0.95) (end -3.6 1.59) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 1.59) (end -2.54 1.59) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 0.95) (end 3.6 0.95) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 0.95) (end 3.6 1.59) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 1.59) (end 2.54 1.59) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 3.49) (end -3.6 3.49) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 3.49) (end -3.6 4.13) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 4.13) (end -2.54 4.13) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 3.49) (end 3.6 3.49) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 3.49) (end 3.6 4.13) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 4.13) (end 2.54 4.13) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 6.03) (end -3.6 6.03) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 6.03) (end -3.6 6.67) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 6.67) (end -2.54 6.67) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 6.03) (end 3.6 6.03) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 6.03) (end 3.6 6.67) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 6.67) (end 2.54 6.67) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 8.57) (end -3.6 8.57) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 8.57) (end -3.6 9.21) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 9.21) (end -2.54 9.21) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 8.57) (end 3.6 8.57) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 8.57) (end 3.6 9.21) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 9.21) (end 2.54 9.21) (layer F.Fab) (width 0.1))
(fp_line (start -2.6 -10.22) (end 2.6 -10.22) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 10.22) (end 2.6 10.22) (layer F.SilkS) (width 0.12))
(fp_line (start -4.04 -9.65) (end -2.6 -9.65) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -10.22) (end -2.6 -9.65) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -10.22) (end 2.6 -9.65) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 9.65) (end -2.6 10.22) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 9.65) (end 2.6 10.22) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -8.13) (end -2.6 -7.11) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -8.13) (end 2.6 -7.11) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -5.59) (end -2.6 -4.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -5.59) (end 2.6 -4.57) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -3.05) (end -2.6 -2.03) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -3.05) (end 2.6 -2.03) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -0.51) (end -2.6 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -0.51) (end 2.6 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 2.03) (end -2.6 3.05) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 2.03) (end 2.6 3.05) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 4.57) (end -2.6 5.59) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 4.57) (end 2.6 5.59) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 7.11) (end -2.6 8.13) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 7.11) (end 2.6 8.13) (layer F.SilkS) (width 0.12))
(fp_line (start -5.9 -10.7) (end -5.9 10.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.9 10.7) (end 5.9 10.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.9 10.7) (end 5.9 -10.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.9 -10.7) (end -5.9 -10.7) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at -2.525 -8.89) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 2 smd rect (at 2.525 -8.89) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(J6-Pad2)"))
(pad 3 smd rect (at -2.525 -6.35) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 4 smd rect (at 2.525 -6.35) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 46 "Net-(J6-Pad4)"))
(pad 5 smd rect (at -2.525 -3.81) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 6 smd rect (at 2.525 -3.81) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 47 "Net-(J6-Pad6)"))
(pad 7 smd rect (at -2.525 -1.27) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 8 smd rect (at 2.525 -1.27) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 48 "Net-(J6-Pad8)"))
(pad 9 smd rect (at -2.525 1.27) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 10 smd rect (at 2.525 1.27) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 49 "Net-(J6-Pad10)"))
(pad 11 smd rect (at -2.525 3.81) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 12 smd rect (at 2.525 3.81) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 50 "Net-(J6-Pad12)"))
(pad 13 smd rect (at -2.525 6.35) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 14 smd rect (at 2.525 6.35) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 51 "Net-(J6-Pad14)"))
(pad 15 smd rect (at -2.525 8.89) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 16 smd rect (at 2.525 8.89) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 52 "Net-(J6-Pad16)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x08_P2.54mm_Vertical_SMD.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA674C0)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 128.27)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B738E50)
(fp_text reference Q1 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 53 "Net-(Q1-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 32 "Net-(J4-Pad1)"))
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA674DA)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 123.19)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B73B28F)
(fp_text reference Q2 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 33 "Net-(J4-Pad2)"))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 54 "Net-(Q2-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA674F4)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 118.11)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B73B2EB)
(fp_text reference Q3 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 55 "Net-(Q3-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 34 "Net-(J4-Pad3)"))
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA6750E)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 113.03)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B741988)
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(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
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(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 35 "Net-(J4-Pad6)"))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 56 "Net-(Q4-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA67528)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 96.52)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B74198E)
(fp_text reference Q5 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 57 "Net-(Q5-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 36 "Net-(J4-Pad7)"))
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA67542)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 91.44)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B741994)
(fp_text reference Q6 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 37 "Net-(J4-Pad8)"))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 58 "Net-(Q6-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA6755C)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 86.36)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B741B64)
(fp_text reference Q7 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 43 "Net-(J5-Pad1)"))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 59 "Net-(Q7-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA67576)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 81.28)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B741B6A)
(fp_text reference Q8 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 3.135) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 60 "Net-(Q8-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 42 "Net-(J5-Pad2)"))
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA67590)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 63.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B74524C)
(fp_text reference Q9 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 41 "Net-(J5-Pad3)"))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 61 "Net-(Q9-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA675AA)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 58.42)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B745252)
(fp_text reference Q10 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 62 "Net-(Q10-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 40 "Net-(J5-Pad6)"))
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5BB69736) (tstamp 5BA675C4)
(at 109.22 53.34)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B745258)
(fp_text reference Q11 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 39 "Net-(J5-Pad7)"))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 63 "Net-(Q11-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BA675DE)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 48.26)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B74525E)
(fp_text reference Q12 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 64 "Net-(Q12-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 38 "Net-(J5-Pad8)"))
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67600)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.6475 125.73)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BBE0F70)
(attr smd)
(fp_text reference R2 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 5 "Net-(D1-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67611)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.6475 120.65)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06A12)
(attr smd)
(fp_text reference R3 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 8 "Net-(D2-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67622)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.6475 115.57)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06ACC)
(attr smd)
(fp_text reference R4 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 9 "Net-(D3-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67633)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.6475 110.49)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06B88)
(attr smd)
(fp_text reference R5 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 12 "Net-(D4-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67644)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.495 93.98)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06C3C)
(attr smd)
(fp_text reference R6 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 14 "Net-(D5-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67655)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.495 88.9)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06CF2)
(attr smd)
(fp_text reference R7 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 15 "Net-(D6-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67666)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.495 83.82)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06DAA)
(attr smd)
(fp_text reference R8 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 18 "Net-(D7-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67677)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.495 78.74)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06E64)
(attr smd)
(fp_text reference R9 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 19 "Net-(D8-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67688)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.3425 60.96)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06F20)
(attr smd)
(fp_text reference R10 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 21 "Net-(D9-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67699)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.3425 55.88)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06FDE)
(attr smd)
(fp_text reference R11 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 24 "Net-(D10-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA676AA)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.3425 50.8)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC0709E)
(attr smd)
(fp_text reference R12 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 25 "Net-(D11-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA676BB)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.3425 45.72)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC07160)
(attr smd)
(fp_text reference R13 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 28 "Net-(D12-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA676CC)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 128.27)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA1F194)
(attr smd)
(fp_text reference R14 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 53 "Net-(Q1-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA676DD)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 123.19)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA4049C)
(attr smd)
(fp_text reference R15 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 54 "Net-(Q2-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA676EE)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 118.11)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40536)
(attr smd)
(fp_text reference R16 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 55 "Net-(Q3-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA676FF)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 125.73 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BDE0369)
(attr smd)
(fp_text reference R17 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 67 "Net-(R17-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67710)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 113.03)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA405D2)
(attr smd)
(fp_text reference R18 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 56 "Net-(Q4-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67721)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 120.65 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A65F)
(attr smd)
(fp_text reference R19 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 68 "Net-(R19-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67732)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 96.52)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40670)
(attr smd)
(fp_text reference R20 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 57 "Net-(Q5-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67743)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 115.57 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A72D)
(attr smd)
(fp_text reference R21 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 69 "Net-(R21-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67754)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 91.44)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40710)
(attr smd)
(fp_text reference R22 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 58 "Net-(Q6-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67765)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 110.49 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A801)
(attr smd)
(fp_text reference R23 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 70 "Net-(R23-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5BB69854) (tstamp 5BA67776)
(at 121.92 86.36)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA407B2)
(attr smd)
(fp_text reference R24 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 59 "Net-(Q7-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67787)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 93.98 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A8CB)
(attr smd)
(fp_text reference R25 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 71 "Net-(R25-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67798)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 81.28)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40856)
(attr smd)
(fp_text reference R26 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 60 "Net-(Q8-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA677A9)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 88.9 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A99B)
(attr smd)
(fp_text reference R27 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 72 "Net-(R27-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA677BA)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 63.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40900)
(attr smd)
(fp_text reference R28 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 61 "Net-(Q9-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA677CB)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 83.82 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0AA69)
(attr smd)
(fp_text reference R29 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 73 "Net-(R29-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA677DC)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 58.42)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA409A8)
(attr smd)
(fp_text reference R30 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 62 "Net-(Q10-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA677ED)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0AB39)
(attr smd)
(fp_text reference R31 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 74 "Net-(R31-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA677FE)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 53.34)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40A52)
(attr smd)
(fp_text reference R32 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 63 "Net-(Q11-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA6780F)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 60.96 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0AC0F)
(attr smd)
(fp_text reference R33 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 75 "Net-(R33-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67820)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 48.26)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40C02)
(attr smd)
(fp_text reference R34 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 64 "Net-(Q12-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67831)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 55.88 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0ACE7)
(attr smd)
(fp_text reference R35 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 76 "Net-(R35-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67842)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 50.8 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0ADBD)
(attr smd)
(fp_text reference R36 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 77 "Net-(R36-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BA67853)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 45.72 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0AE95)
(attr smd)
(fp_text reference R37 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 78 "Net-(R37-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA67868)
route more pcb
2018-08-26 20:13:25 +00:00
(at 175.26 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5BC8AA0E)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference TP1 (at 0 -2.33 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 79 "Net-(TP1-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA6787D)
route more pcb
2018-08-26 20:13:25 +00:00
(at 172.72 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5BCC7A69)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference TP2 (at 0 -2.33 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 80 "Net-(TP2-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA67892)
route more pcb
2018-08-26 20:13:25 +00:00
(at 170.18 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5BCC7AF5)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference TP3 (at 0 -2.33 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 81 "Net-(TP3-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA678A7)
route more pcb
2018-08-26 20:13:25 +00:00
(at 167.64 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5BCC7B87)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference TP4 (at 0 -2.33 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 82 "Net-(TP4-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA678BC)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 48.26)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED4F4)
(fp_text reference TP5 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 83 "Net-(TP5-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA678D1)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 53.34)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED456)
(fp_text reference TP6 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 84 "Net-(TP6-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA678E6)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 63.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED27C)
(fp_text reference TP7 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 85 "Net-(TP7-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA678FB)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 58.42)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED310)
(fp_text reference TP8 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 86 "Net-(TP8-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA67910)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 81.28 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED108)
(fp_text reference TP9 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 87 "Net-(TP9-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA67925)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 123.19 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECC75)
(fp_text reference TP10 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 88 "Net-(TP10-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA6793A)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 118.11 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECD15)
(fp_text reference TP11 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(TP11-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA6794F)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 113.03 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECD9F)
(fp_text reference TP12 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 90 "Net-(TP12-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA67964)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 96.52 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECE31)
(fp_text reference TP13 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 91 "Net-(TP13-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA67979)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 91.44 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECFCE)
(fp_text reference TP14 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(TP14-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA6798E)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 86.36 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED072)
(fp_text reference TP15 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 93 "Net-(TP15-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BA679A3)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 128.27 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECA8C)
(fp_text reference TP16 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 94 "Net-(TP16-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-16_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5BA679F8)
(at 139.7 128.27 180)
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5B7353E2)
(fp_text reference U2 (at 3.81 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LTV-847 (at 3.81 20.11 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 8.89 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 19.3) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 19.3) (end 8.7 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 16 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 "Net-(Q1-Pad3)"))
(pad 8 thru_hole oval (at 0 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(D4-Pad2)"))
(pad 15 thru_hole oval (at 7.62 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 67 "Net-(R17-Pad1)"))
(pad 7 thru_hole oval (at 0 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(TP12-Pad1)"))
(pad 14 thru_hole oval (at 7.62 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(Q2-Pad3)"))
(pad 6 thru_hole oval (at 0 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(D3-Pad2)"))
(pad 13 thru_hole oval (at 7.62 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 68 "Net-(R19-Pad1)"))
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(TP11-Pad1)"))
(pad 12 thru_hole oval (at 7.62 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 55 "Net-(Q3-Pad3)"))
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(D2-Pad2)"))
(pad 11 thru_hole oval (at 7.62 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 69 "Net-(R21-Pad1)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 88 "Net-(TP10-Pad1)"))
(pad 10 thru_hole oval (at 7.62 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 56 "Net-(Q4-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(D1-Pad2)"))
(pad 9 thru_hole oval (at 7.62 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 70 "Net-(R23-Pad1)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 94 "Net-(TP16-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-16_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5BA67A1C)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 139.7 96.52 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5B733EB2)
(fp_text reference U3 (at 3.81 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LTV-847 (at 3.81 20.11 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 19.3) (end 8.7 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 19.3) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 8.89 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(TP13-Pad1)"))
(pad 9 thru_hole oval (at 7.62 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 74 "Net-(R31-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(D5-Pad2)"))
(pad 10 thru_hole oval (at 7.62 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 60 "Net-(Q8-Pad3)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(TP14-Pad1)"))
(pad 11 thru_hole oval (at 7.62 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 73 "Net-(R29-Pad1)"))
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(D6-Pad2)"))
(pad 12 thru_hole oval (at 7.62 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 59 "Net-(Q7-Pad3)"))
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(TP15-Pad1)"))
(pad 13 thru_hole oval (at 7.62 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 72 "Net-(R27-Pad1)"))
(pad 6 thru_hole oval (at 0 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(D7-Pad2)"))
(pad 14 thru_hole oval (at 7.62 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 58 "Net-(Q6-Pad3)"))
(pad 7 thru_hole oval (at 0 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 87 "Net-(TP9-Pad1)"))
(pad 15 thru_hole oval (at 7.62 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 71 "Net-(R25-Pad1)"))
(pad 8 thru_hole oval (at 0 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(D8-Pad2)"))
(pad 16 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 57 "Net-(Q5-Pad3)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Package_DIP:DIP-16_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5BA67A40)
(at 139.7 63.5 180)
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5B745234)
(fp_text reference U4 (at 3.81 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LTV-847 (at 3.81 20.11 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 19.3) (end 8.7 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 19.3) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 8.89 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 85 "Net-(TP7-Pad1)"))
(pad 9 thru_hole oval (at 7.62 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 78 "Net-(R37-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 "Net-(D9-Pad2)"))
(pad 10 thru_hole oval (at 7.62 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 64 "Net-(Q12-Pad3)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(TP8-Pad1)"))
(pad 11 thru_hole oval (at 7.62 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 77 "Net-(R36-Pad1)"))
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(D10-Pad2)"))
(pad 12 thru_hole oval (at 7.62 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 63 "Net-(Q11-Pad3)"))
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(TP6-Pad1)"))
(pad 13 thru_hole oval (at 7.62 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 "Net-(R35-Pad1)"))
(pad 6 thru_hole oval (at 0 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(D11-Pad2)"))
(pad 14 thru_hole oval (at 7.62 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 62 "Net-(Q10-Pad3)"))
(pad 7 thru_hole oval (at 0 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 83 "Net-(TP5-Pad1)"))
(pad 15 thru_hole oval (at 7.62 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 75 "Net-(R33-Pad1)"))
(pad 8 thru_hole oval (at 0 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(D12-Pad2)"))
(pad 16 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 61 "Net-(Q9-Pad3)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(gr_text "pneumatik ventil-io\n(c) Philipp Kramer\nRev. 2018-01" (at 187.96 124.46) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
add ground and power planes
2018-08-28 21:14:49 +00:00
(gr_line (start 70 140) (end 70 40) (layer Edge.Cuts) (width 0.2))
(gr_line (start 230 140) (end 70 140) (layer Edge.Cuts) (width 0.2))
(gr_line (start 230 40) (end 230 140) (layer Edge.Cuts) (width 0.2))
(gr_line (start 70 40) (end 230 40) (layer Edge.Cuts) (width 0.2))
start pcb layout
2018-08-26 19:54:32 +00:00
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 184.785 101.4475) (end 184.6325 101.6) (width 0.5) (layer F.Cu) (net 1))
add ground and power planes
2018-08-28 21:14:49 +00:00
(segment (start 184.785 98.68) (end 184.785 101.4475) (width 0.5) (layer F.Cu) (net 1))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 211.08 53.6) (end 207.645 53.6) (width 0.5) (layer F.Cu) (net 1))
(segment (start 216.97 59.49) (end 211.08 53.6) (width 0.5) (layer F.Cu) (net 1))
(segment (start 220.5 59.49) (end 216.97 59.49) (width 0.5) (layer F.Cu) (net 1))
(segment (start 186.055 101.4475) (end 186.2075 101.6) (width 0.5) (layer F.Cu) (net 2))
add ground and power planes
2018-08-28 21:14:49 +00:00
(segment (start 186.055 98.68) (end 186.055 101.4475) (width 0.5) (layer F.Cu) (net 2))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 220.36 48) (end 208.695 48) (width 0.5) (layer F.Cu) (net 2))
(segment (start 208.695 48) (end 207.645 48) (width 0.5) (layer F.Cu) (net 2))
(segment (start 223 50.64) (end 220.36 48) (width 0.5) (layer F.Cu) (net 2))
(segment (start 223 51.99) (end 223 50.64) (width 0.5) (layer F.Cu) (net 2))
add ground and power planes
2018-08-28 21:14:49 +00:00
(segment (start 186.2075 101.6) (end 186.2075 103.6575) (width 0.5) (layer F.Cu) (net 2))
(segment (start 186.2075 103.6575) (end 186.69 104.14) (width 0.5) (layer F.Cu) (net 2))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(via (at 186.69 104.14) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(via (at 153.67 45.72) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(segment (start 151.13 45.72) (end 153.67 45.72) (width 0.5) (layer F.Cu) (net 2))
(segment (start 151.13 50.8) (end 153.67 50.8) (width 0.5) (layer F.Cu) (net 2))
(via (at 153.67 50.8) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(segment (start 151.13 55.88) (end 153.67 55.88) (width 0.5) (layer F.Cu) (net 2))
(via (at 153.67 55.88) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(segment (start 151.13 60.96) (end 153.67 60.96) (width 0.5) (layer F.Cu) (net 2))
(via (at 153.67 60.96) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 207.645 48) (end 207.645 46) (width 0.5) (layer F.Cu) (net 2))
(segment (start 207.645 46) (end 207.645 44.45) (width 0.5) (layer F.Cu) (net 2))
(via (at 207.645 44.45) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 194.945 43.43) (end 194.945 45.72) (width 0.5) (layer F.Cu) (net 2))
(via (at 194.945 45.72) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(via (at 186.055 45.72) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(segment (start 186.055 43.43) (end 186.055 45.72) (width 0.5) (layer F.Cu) (net 2))
(segment (start 177.165 43.43) (end 177.165 45.72) (width 0.5) (layer F.Cu) (net 2))
(via (at 177.165 45.72) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(via (at 153.035 125.73) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(segment (start 151.435 125.73) (end 153.035 125.73) (width 0.5) (layer F.Cu) (net 2))
(segment (start 151.435 120.65) (end 153.035 120.65) (width 0.5) (layer F.Cu) (net 2))
(via (at 153.035 120.65) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(segment (start 151.435 115.57) (end 153.035 115.57) (width 0.5) (layer F.Cu) (net 2))
(via (at 153.035 115.57) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(segment (start 151.435 110.49) (end 153.035 110.49) (width 0.5) (layer F.Cu) (net 2))
(via (at 153.035 110.49) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(via (at 153.035 93.98) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(via (at 153.035 88.9) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(via (at 153.035 83.82) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(via (at 153.035 78.74) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 2))
(segment (start 151.13 78.74) (end 153.035 78.74) (width 0.5) (layer F.Cu) (net 2))
add ground and power planes
2018-08-28 21:14:49 +00:00
(segment (start 223 126.99) (end 220.5 124.49) (width 2) (layer B.Cu) (net 3))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 200.025 135.255) (end 117.475 135.255) (width 2) (layer B.Cu) (net 3))
(segment (start 117.475 135.255) (end 116.84 134.62) (width 2) (layer B.Cu) (net 3))
(segment (start 220.5 124.49) (end 210.79 124.49) (width 2) (layer B.Cu) (net 3))
(segment (start 210.79 124.49) (end 200.025 135.255) (width 2) (layer B.Cu) (net 3))
(via (at 125.095 45.72) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 50.8) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 55.88) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 60.96) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 78.74) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 83.82) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 88.9) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 93.98) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 110.49) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 115.57) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 120.65) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(via (at 125.095 125.73) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 3))
(segment (start 125.095 125.73) (end 126.2125 125.73) (width 0.35) (layer F.Cu) (net 3))
(segment (start 126.2125 120.65) (end 125.095 120.65) (width 0.35) (layer F.Cu) (net 3))
(segment (start 125.095 115.57) (end 126.2125 115.57) (width 0.35) (layer F.Cu) (net 3))
(segment (start 126.2125 110.49) (end 125.095 110.49) (width 0.35) (layer F.Cu) (net 3))
(segment (start 126.2125 45.72) (end 125.095 45.72) (width 0.35) (layer F.Cu) (net 3))
(segment (start 125.095 50.8) (end 126.2125 50.8) (width 0.35) (layer F.Cu) (net 3))
(segment (start 126.2125 55.88) (end 125.095 55.88) (width 0.35) (layer F.Cu) (net 3))
(segment (start 126.2125 60.96) (end 125.095 60.96) (width 0.35) (layer F.Cu) (net 3))
(segment (start 125.095 78.74) (end 126.2125 78.74) (width 0.35) (layer F.Cu) (net 3))
(segment (start 125.095 83.82) (end 126.2125 83.82) (width 0.35) (layer F.Cu) (net 3))
(segment (start 125.095 88.9) (end 126.2125 88.9) (width 0.35) (layer F.Cu) (net 3))
(segment (start 125.095 93.98) (end 126.2125 93.98) (width 0.35) (layer F.Cu) (net 3))
add ground and power planes
2018-08-28 21:14:49 +00:00
(segment (start 223 121.99) (end 220.5 119.49) (width 2) (layer F.Cu) (net 4))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 200.025 135.255) (end 117.475 135.255) (width 2) (layer F.Cu) (net 4))
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(segment (start 220.5 119.49) (end 215.79 119.49) (width 2) (layer F.Cu) (net 4))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 215.79 119.49) (end 200.025 135.255) (width 2) (layer F.Cu) (net 4))
(segment (start 117.475 135.255) (end 97.155 135.255) (width 0.35) (layer F.Cu) (net 4))
(segment (start 97.155 135.255) (end 95.885 133.985) (width 0.35) (layer F.Cu) (net 4))
(segment (start 109.22 53.34) (end 109.22 54.59) (width 0.35) (layer F.Cu) (net 4))
(segment (start 109.22 99.695) (end 95.885 99.695) (width 0.35) (layer F.Cu) (net 4))
(segment (start 95.885 133.985) (end 95.885 99.695) (width 0.35) (layer F.Cu) (net 4))
(segment (start 109.22 99.695) (end 109.22 128.27) (width 0.35) (layer F.Cu) (net 4))
(segment (start 95.885 99.695) (end 95.885 48.26) (width 0.35) (layer F.Cu) (net 4))
(segment (start 109.22 54.59) (end 109.22 99.695) (width 0.35) (layer F.Cu) (net 4))
(segment (start 109.22 99.695) (end 121.285 99.695) (width 0.35) (layer F.Cu) (net 4))
(segment (start 121.285 99.695) (end 121.1325 99.695) (width 0.35) (layer F.Cu) (net 4))
(segment (start 121.1325 128.27) (end 121.1325 99.695) (width 0.35) (layer F.Cu) (net 4))
(segment (start 121.1325 99.695) (end 121.1325 48.26) (width 0.35) (layer F.Cu) (net 4))
(segment (start 145.7175 125.73) (end 149.86 125.73) (width 0.35) (layer F.Cu) (net 5))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 139.7 125.73) (end 142.5725 125.73) (width 0.35) (layer F.Cu) (net 6))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 142.5725 125.73) (end 143.8425 125.73) (width 0.35) (layer F.Cu) (net 6))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 142.5725 120.65) (end 139.7 120.65) (width 0.35) (layer F.Cu) (net 7))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 142.5725 120.65) (end 143.8425 120.65) (width 0.35) (layer F.Cu) (net 7))
(segment (start 149.86 120.65) (end 145.7175 120.65) (width 0.35) (layer F.Cu) (net 8))
(segment (start 149.86 115.57) (end 145.7175 115.57) (width 0.35) (layer F.Cu) (net 9))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 142.5725 115.57) (end 139.7 115.57) (width 0.35) (layer F.Cu) (net 10))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 142.5725 115.57) (end 143.8425 115.57) (width 0.35) (layer F.Cu) (net 10))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 142.5725 110.49) (end 139.7 110.49) (width 0.35) (layer F.Cu) (net 11))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 142.5725 110.49) (end 143.8425 110.49) (width 0.35) (layer F.Cu) (net 11))
(segment (start 149.86 110.49) (end 146.05 110.49) (width 0.35) (layer F.Cu) (net 12))
(segment (start 146.05 110.49) (end 145.7175 110.49) (width 0.35) (layer F.Cu) (net 12))
(segment (start 142.24 93.98) (end 143.8425 93.98) (width 0.35) (layer F.Cu) (net 13))
(segment (start 142.24 93.98) (end 139.7 93.98) (width 0.35) (layer F.Cu) (net 13))
(segment (start 142.5725 93.98) (end 142.24 93.98) (width 0.35) (layer F.Cu) (net 13))
(segment (start 149.7075 93.98) (end 145.7175 93.98) (width 0.35) (layer F.Cu) (net 14))
(segment (start 145.664998 88.9) (end 149.514999 88.9) (width 0.35) (layer F.Cu) (net 15))
(segment (start 142.24 88.9) (end 143.789998 88.9) (width 0.35) (layer F.Cu) (net 16))
(segment (start 142.24 88.9) (end 142.519998 88.9) (width 0.35) (layer F.Cu) (net 16))
(segment (start 139.7 88.9) (end 142.24 88.9) (width 0.35) (layer F.Cu) (net 16))
(segment (start 142.24 83.82) (end 143.8425 83.82) (width 0.35) (layer F.Cu) (net 17))
(segment (start 142.24 83.82) (end 139.7 83.82) (width 0.35) (layer F.Cu) (net 17))
(segment (start 142.5725 83.82) (end 142.24 83.82) (width 0.35) (layer F.Cu) (net 17))
(segment (start 149.555 83.82) (end 145.7175 83.82) (width 0.35) (layer F.Cu) (net 18))
(segment (start 145.7175 78.74) (end 149.555 78.74) (width 0.35) (layer F.Cu) (net 19))
(segment (start 142.24 78.74) (end 143.8425 78.74) (width 0.35) (layer F.Cu) (net 20))
(segment (start 142.24 78.74) (end 142.5725 78.74) (width 0.35) (layer F.Cu) (net 20))
(segment (start 139.7 78.74) (end 142.24 78.74) (width 0.35) (layer F.Cu) (net 20))
(segment (start 145.7175 60.96) (end 149.555 60.96) (width 0.35) (layer F.Cu) (net 21))
(segment (start 140.97 60.96) (end 143.8425 60.96) (width 0.35) (layer F.Cu) (net 22))
(segment (start 140.97 55.88) (end 143.51 55.88) (width 0.35) (layer F.Cu) (net 23))
(segment (start 143.51 55.88) (end 143.8425 55.88) (width 0.35) (layer F.Cu) (net 23))
(segment (start 145.7175 55.88) (end 149.555 55.88) (width 0.35) (layer F.Cu) (net 24))
(segment (start 149.555 50.8) (end 145.7175 50.8) (width 0.35) (layer F.Cu) (net 25))
(segment (start 143.8425 50.8) (end 140.97 50.8) (width 0.35) (layer F.Cu) (net 26))
(segment (start 140.97 45.72) (end 143.8425 45.72) (width 0.35) (layer F.Cu) (net 27))
(segment (start 145.7175 45.72) (end 149.555 45.72) (width 0.35) (layer F.Cu) (net 28))
(segment (start 187.325 51.435) (end 188.595 52.705) (width 0.35) (layer F.Cu) (net 29))
(segment (start 180.975 51.435) (end 187.325 51.435) (width 0.35) (layer F.Cu) (net 29))
(segment (start 188.595 52.705) (end 188.595 89.28) (width 0.35) (layer F.Cu) (net 29))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 179.705 46.74) (end 179.705 50.165) (width 0.35) (layer F.Cu) (net 29))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 179.705 50.165) (end 180.975 51.435) (width 0.35) (layer F.Cu) (net 29))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 189.865 89.28) (end 189.865 52.705) (width 0.35) (layer F.Cu) (net 30))
(segment (start 188.595 51.435) (end 188.595 46.74) (width 0.35) (layer F.Cu) (net 30))
(segment (start 189.865 52.705) (end 188.595 51.435) (width 0.35) (layer F.Cu) (net 30))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 192.405 51.435) (end 196.215 51.435) (width 0.35) (layer F.Cu) (net 31))
(segment (start 197.485 50.165) (end 197.485 46.74) (width 0.35) (layer F.Cu) (net 31))
(segment (start 196.215 51.435) (end 197.485 50.165) (width 0.35) (layer F.Cu) (net 31))
(segment (start 191.135 89.28) (end 191.135 52.705) (width 0.35) (layer F.Cu) (net 31))
(segment (start 191.135 52.705) (end 192.405 51.435) (width 0.35) (layer F.Cu) (net 31))
(segment (start 199.405 61.71) (end 199.405 63.5) (width 0.35) (layer F.Cu) (net 44) (tstamp 5BB6B17A))
(segment (start 199.405 60.96) (end 199.405 61.71) (width 0.35) (layer F.Cu) (net 44) (tstamp 5BB6B177))
(segment (start 199.405 63.5) (end 199.405 66.04) (width 0.35) (layer F.Cu) (net 44) (tstamp 5BB6B174))
(segment (start 199.405 66.04) (end 199.405 68.58) (width 0.35) (layer F.Cu) (net 44) (tstamp 5BB6B171))
(segment (start 199.405 68.58) (end 199.405 71.12) (width 0.35) (layer F.Cu) (net 44) (tstamp 5BB6B16E))
(segment (start 199.405 71.12) (end 199.405 73.66) (width 0.35) (layer F.Cu) (net 44) (tstamp 5BB6B16B))
(segment (start 199.405 73.66) (end 199.405 76.2) (width 0.35) (layer F.Cu) (net 44) (tstamp 5BB6B042))
(segment (start 199.405 76.2) (end 199.405 78.74) (width 0.35) (layer F.Cu) (net 44) (tstamp 5BB6B03F))
(segment (start 198.12 92.71) (end 188.595 92.71) (width 0.35) (layer F.Cu) (net 44))
(segment (start 187.325 93.98) (end 187.325 98.68) (width 0.35) (layer F.Cu) (net 44))
(segment (start 199.405 77.47) (end 199.405 91.425) (width 0.35) (layer F.Cu) (net 44))
(segment (start 188.595 92.71) (end 187.325 93.98) (width 0.35) (layer F.Cu) (net 44))
(segment (start 199.405 91.425) (end 198.12 92.71) (width 0.35) (layer F.Cu) (net 44))
(segment (start 204.455 60.96) (end 209.55 60.96) (width 0.35) (layer F.Cu) (net 45) (tstamp 5BB6B03C))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 210.58 61.99) (end 223 61.99) (width 0.35) (layer F.Cu) (net 45))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 209.55 60.96) (end 210.58 61.99) (width 0.35) (layer F.Cu) (net 45) (tstamp 5BB6B039))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 220.5 64.49) (end 210.54 64.49) (width 0.35) (layer F.Cu) (net 46))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 209.55 63.5) (end 204.455 63.5) (width 0.35) (layer F.Cu) (net 46) (tstamp 5BB6B036))
(segment (start 210.54 64.49) (end 209.55 63.5) (width 0.35) (layer F.Cu) (net 46) (tstamp 5BB6B033))
(segment (start 204.455 66.04) (end 206.28 66.04) (width 0.35) (layer F.Cu) (net 47) (tstamp 5BB6B030))
(segment (start 204.455 66.04) (end 209.55 66.04) (width 0.35) (layer F.Cu) (net 47) (tstamp 5BB6B02D))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 210.5 66.99) (end 223 66.99) (width 0.35) (layer F.Cu) (net 47))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 209.55 66.04) (end 210.5 66.99) (width 0.35) (layer F.Cu) (net 47) (tstamp 5BB6B02A))
(segment (start 204.455 68.58) (end 209.55 68.58) (width 0.35) (layer F.Cu) (net 48) (tstamp 5BB6B027))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 210.46 69.49) (end 220.5 69.49) (width 0.35) (layer F.Cu) (net 48))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 209.55 68.58) (end 210.46 69.49) (width 0.35) (layer F.Cu) (net 48) (tstamp 5BB6B024))
(segment (start 204.455 71.12) (end 209.55 71.12) (width 0.35) (layer F.Cu) (net 49) (tstamp 5BB6B021))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 210.42 71.99) (end 223 71.99) (width 0.35) (layer F.Cu) (net 49))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 209.55 71.12) (end 210.42 71.99) (width 0.35) (layer F.Cu) (net 49) (tstamp 5BB6B01E))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 220.5 74.49) (end 211.65 74.49) (width 0.35) (layer F.Cu) (net 50))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 210.82 73.66) (end 204.455 73.66) (width 0.35) (layer F.Cu) (net 50) (tstamp 5BB6B01B))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 211.65 74.49) (end 210.82 73.66) (width 0.35) (layer F.Cu) (net 50))
(segment (start 223 76.99) (end 210.34 76.99) (width 0.35) (layer F.Cu) (net 51))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 209.55 76.2) (end 204.455 76.2) (width 0.35) (layer F.Cu) (net 51) (tstamp 5BB6B018))
(segment (start 210.34 76.99) (end 209.55 76.2) (width 0.35) (layer F.Cu) (net 51) (tstamp 5BB6B015))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 220.5 79.49) (end 209.03 79.49) (width 0.35) (layer F.Cu) (net 52))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 208.28 78.74) (end 204.455 78.74) (width 0.35) (layer F.Cu) (net 52) (tstamp 5BB6B012))
(segment (start 209.03 79.49) (end 208.28 78.74) (width 0.35) (layer F.Cu) (net 52) (tstamp 5BB6B00F))
(via (at 122.555 126.365) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 53))
(segment (start 114.3 127) (end 114.3 128.27) (width 0.35) (layer B.Cu) (net 53))
(segment (start 122.555 126.365) (end 114.935 126.365) (width 0.35) (layer B.Cu) (net 53))
(segment (start 114.935 126.365) (end 114.3 127) (width 0.35) (layer B.Cu) (net 53))
(segment (start 129.0575 128.27) (end 132.08 128.27) (width 0.35) (layer F.Cu) (net 53))
(segment (start 122.7075 128.27) (end 129.0575 128.27) (width 0.35) (layer F.Cu) (net 53))
(segment (start 122.7075 126.5175) (end 122.555 126.365) (width 0.35) (layer F.Cu) (net 53))
(segment (start 122.7075 128.27) (end 122.7075 126.5175) (width 0.35) (layer F.Cu) (net 53))
(segment (start 129.0575 123.19) (end 132.08 123.19) (width 0.35) (layer F.Cu) (net 54))
(segment (start 122.7075 123.19) (end 129.0575 123.19) (width 0.35) (layer F.Cu) (net 54))
(segment (start 100.965 123.19) (end 100.965 121.92) (width 0.35) (layer B.Cu) (net 54))
(segment (start 100.965 121.92) (end 101.6 121.285) (width 0.35) (layer B.Cu) (net 54))
(segment (start 101.6 121.285) (end 120.015 121.285) (width 0.35) (layer B.Cu) (net 54))
(segment (start 120.015 121.285) (end 122.555 121.285) (width 0.35) (layer B.Cu) (net 54))
(via (at 122.555 121.285) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 54))
(segment (start 122.7075 123.19) (end 122.7075 121.4375) (width 0.35) (layer F.Cu) (net 54))
(segment (start 122.7075 121.4375) (end 122.555 121.285) (width 0.35) (layer F.Cu) (net 54))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 129.0575 118.11) (end 132.08 118.11) (width 0.35) (layer F.Cu) (net 55))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 127.7875 118.11) (end 122.7075 118.11) (width 0.35) (layer F.Cu) (net 55))
(segment (start 114.3 118.11) (end 114.3 116.84) (width 0.35) (layer B.Cu) (net 55))
(segment (start 114.3 116.84) (end 114.935 116.205) (width 0.35) (layer B.Cu) (net 55))
(segment (start 114.935 116.205) (end 122.555 116.205) (width 0.35) (layer B.Cu) (net 55))
(via (at 122.555 116.205) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 55))
(segment (start 122.7075 116.3575) (end 122.555 116.205) (width 0.35) (layer F.Cu) (net 55))
(segment (start 122.7075 118.11) (end 122.7075 116.3575) (width 0.35) (layer F.Cu) (net 55))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 129.0575 113.03) (end 132.08 113.03) (width 0.35) (layer F.Cu) (net 56))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 122.7075 113.03) (end 129.0575 113.03) (width 0.35) (layer F.Cu) (net 56))
(segment (start 100.965 113.03) (end 100.965 111.76) (width 0.35) (layer B.Cu) (net 56))
(segment (start 100.965 111.76) (end 101.6 111.125) (width 0.35) (layer B.Cu) (net 56))
(segment (start 101.6 111.125) (end 122.555 111.125) (width 0.35) (layer B.Cu) (net 56))
(via (at 122.555 111.125) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 56))
(segment (start 122.7075 113.03) (end 122.7075 111.2775) (width 0.35) (layer F.Cu) (net 56))
(segment (start 122.7075 111.2775) (end 122.555 111.125) (width 0.35) (layer F.Cu) (net 56))
(segment (start 122.7075 96.52) (end 127.7875 96.52) (width 0.35) (layer F.Cu) (net 57))
(segment (start 114.3 96.52) (end 114.3 95.25) (width 0.35) (layer B.Cu) (net 57))
(segment (start 114.3 95.25) (end 114.935 94.615) (width 0.35) (layer B.Cu) (net 57))
(segment (start 114.935 94.615) (end 122.555 94.615) (width 0.35) (layer B.Cu) (net 57))
(via (at 122.555 94.615) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 57))
(segment (start 122.7075 96.52) (end 122.7075 94.7675) (width 0.35) (layer F.Cu) (net 57))
(segment (start 122.7075 94.7675) (end 122.555 94.615) (width 0.35) (layer F.Cu) (net 57))
(segment (start 127.7875 96.52) (end 129.54 96.52) (width 0.35) (layer F.Cu) (net 57))
(segment (start 129.0575 96.52) (end 129.54 96.52) (width 0.35) (layer F.Cu) (net 57))
(segment (start 129.54 96.52) (end 132.08 96.52) (width 0.35) (layer F.Cu) (net 57))
(segment (start 100.965 91.44) (end 100.965 90.17) (width 0.35) (layer B.Cu) (net 58))
(segment (start 100.965 90.17) (end 101.6 89.535) (width 0.35) (layer B.Cu) (net 58))
(segment (start 101.6 89.535) (end 122.555 89.535) (width 0.35) (layer B.Cu) (net 58))
(segment (start 129.0575 91.44) (end 132.08 91.44) (width 0.35) (layer F.Cu) (net 58))
(segment (start 122.7075 91.44) (end 129.0575 91.44) (width 0.35) (layer F.Cu) (net 58))
(via (at 122.555 89.535) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 58))
(segment (start 122.7075 91.44) (end 122.7075 89.6875) (width 0.35) (layer F.Cu) (net 58))
(segment (start 122.7075 89.6875) (end 122.555 89.535) (width 0.35) (layer F.Cu) (net 58))
(segment (start 122.7075 86.36) (end 127.7875 86.36) (width 0.35) (layer F.Cu) (net 59))
(segment (start 114.3 86.36) (end 114.3 85.09) (width 0.35) (layer B.Cu) (net 59))
(segment (start 114.3 85.09) (end 114.935 84.455) (width 0.35) (layer B.Cu) (net 59))
(segment (start 114.935 84.455) (end 122.555 84.455) (width 0.35) (layer B.Cu) (net 59))
(via (at 122.555 84.455) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 59))
(segment (start 122.7075 86.36) (end 122.7075 84.6075) (width 0.35) (layer F.Cu) (net 59))
(segment (start 122.7075 84.6075) (end 122.555 84.455) (width 0.35) (layer F.Cu) (net 59))
(segment (start 127.7875 86.36) (end 129.54 86.36) (width 0.35) (layer F.Cu) (net 59))
(segment (start 129.0575 86.36) (end 129.54 86.36) (width 0.35) (layer F.Cu) (net 59))
(segment (start 129.54 86.36) (end 132.08 86.36) (width 0.35) (layer F.Cu) (net 59))
(segment (start 127.7875 81.28) (end 122.7075 81.28) (width 0.35) (layer F.Cu) (net 60))
(segment (start 100.965 81.28) (end 100.965 80.01) (width 0.35) (layer B.Cu) (net 60))
(segment (start 100.965 80.01) (end 101.6 79.375) (width 0.35) (layer B.Cu) (net 60))
(segment (start 101.6 79.375) (end 122.555 79.375) (width 0.35) (layer B.Cu) (net 60))
(segment (start 127.7875 81.28) (end 129.54 81.28) (width 0.35) (layer F.Cu) (net 60))
(segment (start 129.0575 81.28) (end 129.54 81.28) (width 0.35) (layer F.Cu) (net 60))
(segment (start 129.54 81.28) (end 132.08 81.28) (width 0.35) (layer F.Cu) (net 60))
(segment (start 122.7075 81.28) (end 122.7075 79.5275) (width 0.35) (layer F.Cu) (net 60))
(via (at 122.555 79.375) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 60))
(segment (start 122.7075 79.5275) (end 122.555 79.375) (width 0.35) (layer F.Cu) (net 60))
(segment (start 114.3 63.5) (end 114.3 62.23) (width 0.35) (layer B.Cu) (net 61))
(segment (start 114.3 62.23) (end 114.935 61.595) (width 0.35) (layer B.Cu) (net 61))
(segment (start 122.7075 63.5) (end 122.7075 61.7475) (width 0.35) (layer F.Cu) (net 61))
(via (at 122.555 61.595) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 61))
(segment (start 122.7075 61.7475) (end 122.555 61.595) (width 0.35) (layer F.Cu) (net 61))
(segment (start 114.935 61.595) (end 122.555 61.595) (width 0.35) (layer B.Cu) (net 61))
(segment (start 129.0575 63.5) (end 132.08 63.5) (width 0.35) (layer F.Cu) (net 61))
(segment (start 122.7075 63.5) (end 129.0575 63.5) (width 0.35) (layer F.Cu) (net 61))
(segment (start 122.7075 58.42) (end 127.7875 58.42) (width 0.35) (layer F.Cu) (net 62))
(segment (start 100.965 58.42) (end 100.965 57.15) (width 0.35) (layer B.Cu) (net 62))
(segment (start 100.965 57.15) (end 101.6 56.515) (width 0.35) (layer B.Cu) (net 62))
(segment (start 101.6 56.515) (end 122.555 56.515) (width 0.35) (layer B.Cu) (net 62))
(segment (start 127.7875 58.42) (end 129.54 58.42) (width 0.35) (layer F.Cu) (net 62))
(segment (start 132.08 58.42) (end 129.54 58.42) (width 0.35) (layer F.Cu) (net 62))
(segment (start 129.54 58.42) (end 129.0575 58.42) (width 0.35) (layer F.Cu) (net 62))
(via (at 122.555 56.515) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 62))
(segment (start 122.7075 58.42) (end 122.7075 56.6675) (width 0.35) (layer F.Cu) (net 62))
(segment (start 122.7075 56.6675) (end 122.555 56.515) (width 0.35) (layer F.Cu) (net 62))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 132.08 53.34) (end 123.9775 53.34) (width 0.35) (layer F.Cu) (net 63))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 114.3 53.34) (end 114.3 52.07) (width 0.35) (layer B.Cu) (net 63))
(segment (start 114.3 52.07) (end 114.935 51.435) (width 0.35) (layer B.Cu) (net 63))
(segment (start 114.935 51.435) (end 122.555 51.435) (width 0.35) (layer B.Cu) (net 63))
(via (at 122.555 51.435) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 63))
(segment (start 122.7075 53.34) (end 122.7075 51.5875) (width 0.35) (layer F.Cu) (net 63))
(segment (start 122.7075 51.5875) (end 122.555 51.435) (width 0.35) (layer F.Cu) (net 63))
(segment (start 122.7075 53.34) (end 123.9775 53.34) (width 0.35) (layer F.Cu) (net 63))
(segment (start 100.965 48.26) (end 100.965 46.99) (width 0.35) (layer B.Cu) (net 64))
(segment (start 100.965 46.99) (end 101.6 46.355) (width 0.35) (layer B.Cu) (net 64))
(segment (start 101.6 46.355) (end 122.555 46.355) (width 0.35) (layer B.Cu) (net 64))
(via (at 122.555 46.355) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 64))
(segment (start 122.7075 48.26) (end 122.7075 46.5075) (width 0.35) (layer F.Cu) (net 64))
(segment (start 122.7075 46.5075) (end 122.555 46.355) (width 0.35) (layer F.Cu) (net 64))
(segment (start 122.7075 48.26) (end 128.905 48.26) (width 0.35) (layer F.Cu) (net 64))
(segment (start 128.905 48.26) (end 129.54 48.26) (width 0.35) (layer F.Cu) (net 64))
(segment (start 132.08 48.26) (end 129.54 48.26) (width 0.35) (layer F.Cu) (net 64))
(segment (start 129.54 48.26) (end 129.0575 48.26) (width 0.35) (layer F.Cu) (net 64))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 187.325 85.8775) (end 187.325 89.28) (width 0.35) (layer F.Cu) (net 66))
(segment (start 129.0575 125.73) (end 132.08 125.73) (width 0.35) (layer F.Cu) (net 67))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 127.7875 125.73) (end 129.0575 125.73) (width 0.35) (layer F.Cu) (net 67))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 132.08 120.65) (end 129.0575 120.65) (width 0.35) (layer F.Cu) (net 68))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 127.7875 120.65) (end 129.0575 120.65) (width 0.35) (layer F.Cu) (net 68))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 132.08 115.57) (end 129.0575 115.57) (width 0.35) (layer F.Cu) (net 69))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 127.7875 115.57) (end 129.0575 115.57) (width 0.35) (layer F.Cu) (net 69))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 132.08 110.49) (end 129.0575 110.49) (width 0.35) (layer F.Cu) (net 70))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 129.0575 110.49) (end 127.7875 110.49) (width 0.35) (layer F.Cu) (net 70))
(segment (start 127.7875 93.98) (end 129.54 93.98) (width 0.35) (layer F.Cu) (net 71))
(segment (start 132.08 93.98) (end 129.54 93.98) (width 0.35) (layer F.Cu) (net 71))
(segment (start 129.54 93.98) (end 129.0575 93.98) (width 0.35) (layer F.Cu) (net 71))
(segment (start 132.08 88.9) (end 129.0575 88.9) (width 0.35) (layer F.Cu) (net 72))
(segment (start 127.7875 88.9) (end 129.0575 88.9) (width 0.35) (layer F.Cu) (net 72))
(segment (start 127.7875 83.82) (end 129.54 83.82) (width 0.35) (layer F.Cu) (net 73))
(segment (start 132.08 83.82) (end 129.54 83.82) (width 0.35) (layer F.Cu) (net 73))
(segment (start 129.54 83.82) (end 129.0575 83.82) (width 0.35) (layer F.Cu) (net 73))
(segment (start 132.08 78.74) (end 129.54 78.74) (width 0.35) (layer F.Cu) (net 74))
(segment (start 127.7875 78.74) (end 129.54 78.74) (width 0.35) (layer F.Cu) (net 74))
(segment (start 129.54 78.74) (end 129.0575 78.74) (width 0.35) (layer F.Cu) (net 74))
(segment (start 127.7875 60.96) (end 129.54 60.96) (width 0.35) (layer F.Cu) (net 75))
(segment (start 129.0575 60.96) (end 129.54 60.96) (width 0.35) (layer F.Cu) (net 75))
(segment (start 129.54 60.96) (end 132.08 60.96) (width 0.35) (layer F.Cu) (net 75))
(segment (start 127.7875 55.88) (end 129.54 55.88) (width 0.35) (layer F.Cu) (net 76))
(segment (start 129.0575 55.88) (end 129.54 55.88) (width 0.35) (layer F.Cu) (net 76))
(segment (start 129.54 55.88) (end 132.08 55.88) (width 0.35) (layer F.Cu) (net 76))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 129.0575 50.8) (end 132.08 50.8) (width 0.35) (layer F.Cu) (net 77))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 127.7875 50.8) (end 129.0575 50.8) (width 0.35) (layer F.Cu) (net 77))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 129.0575 45.72) (end 132.08 45.72) (width 0.35) (layer F.Cu) (net 78))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 129.0575 45.72) (end 127.7875 45.72) (width 0.35) (layer F.Cu) (net 78))
(segment (start 178.435 89.28) (end 178.435 83.185) (width 0.35) (layer F.Cu) (net 79))
(segment (start 178.435 83.185) (end 177.165 81.915) (width 0.35) (layer F.Cu) (net 79))
(segment (start 177.165 81.915) (end 175.895 81.915) (width 0.35) (layer F.Cu) (net 79))
(segment (start 175.26 81.28) (end 175.26 78.74) (width 0.35) (layer F.Cu) (net 79))
(segment (start 175.895 81.915) (end 175.26 81.28) (width 0.35) (layer F.Cu) (net 79))
(segment (start 172.72 82.55) (end 172.72 78.74) (width 0.35) (layer F.Cu) (net 80))
(segment (start 173.355 83.185) (end 172.72 82.55) (width 0.35) (layer F.Cu) (net 80))
(segment (start 176.53 83.185) (end 173.355 83.185) (width 0.35) (layer F.Cu) (net 80))
(segment (start 177.165 89.28) (end 177.165 83.82) (width 0.35) (layer F.Cu) (net 80))
(segment (start 177.165 83.82) (end 176.53 83.185) (width 0.35) (layer F.Cu) (net 80))
(segment (start 170.815 84.455) (end 170.18 83.82) (width 0.35) (layer F.Cu) (net 81))
(segment (start 175.26 84.455) (end 170.815 84.455) (width 0.35) (layer F.Cu) (net 81))
(segment (start 175.895 89.28) (end 175.895 85.09) (width 0.35) (layer F.Cu) (net 81))
(segment (start 170.18 83.82) (end 170.18 78.74) (width 0.35) (layer F.Cu) (net 81))
(segment (start 175.895 85.09) (end 175.26 84.455) (width 0.35) (layer F.Cu) (net 81))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 167.64 78.74) (end 167.64 79.84) (width 0.35) (layer F.Cu) (net 82))
(segment (start 167.64 80.645) (end 167.64 78.74) (width 0.35) (layer F.Cu) (net 82))
(segment (start 174.625 89.28) (end 174.625 87.63) (width 0.35) (layer F.Cu) (net 82))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 174.625 87.63) (end 174.625 86.36) (width 0.35) (layer F.Cu) (net 82))
(segment (start 174.625 86.36) (end 173.99 85.725) (width 0.35) (layer F.Cu) (net 82))
(segment (start 173.99 85.725) (end 168.275 85.725) (width 0.35) (layer F.Cu) (net 82))
(segment (start 168.275 85.725) (end 167.64 85.09) (width 0.35) (layer F.Cu) (net 82))
(segment (start 167.64 85.09) (end 167.64 80.645) (width 0.35) (layer F.Cu) (net 82))
(segment (start 156.21 48.26) (end 140.97 48.26) (width 0.35) (layer F.Cu) (net 83))
(segment (start 179.705 89.28) (end 179.705 65.405) (width 0.35) (layer F.Cu) (net 83))
(segment (start 140.97 53.34) (end 156.21 53.34) (width 0.35) (layer F.Cu) (net 84))
(segment (start 180.975 89.28) (end 180.975 65.405) (width 0.35) (layer F.Cu) (net 84))
(segment (start 156.21 53.34) (end 157.41 53.34) (width 0.35) (layer F.Cu) (net 84))
(segment (start 156.21 63.5) (end 140.97 63.5) (width 0.35) (layer F.Cu) (net 85))
(segment (start 183.515 87.93) (end 183.515 89.28) (width 0.35) (layer F.Cu) (net 85))
(segment (start 183.515 87.93) (end 183.515 65.405) (width 0.35) (layer F.Cu) (net 85))
(segment (start 156.21 58.42) (end 140.97 58.42) (width 0.35) (layer F.Cu) (net 86))
(segment (start 182.245 65.405) (end 182.245 89.28) (width 0.35) (layer F.Cu) (net 86))
(segment (start 139.7 81.28) (end 154.94 81.28) (width 0.35) (layer F.Cu) (net 87))
(segment (start 156.21 81.28) (end 154.94 81.28) (width 0.35) (layer F.Cu) (net 87))
(segment (start 159.385 81.28) (end 156.21 81.28) (width 0.35) (layer F.Cu) (net 87))
(segment (start 160.655 81.28) (end 159.385 81.28) (width 0.35) (layer F.Cu) (net 87))
(segment (start 183.515 94.615) (end 181.61 92.71) (width 0.35) (layer F.Cu) (net 87))
(segment (start 161.925 92.71) (end 161.29 92.075) (width 0.35) (layer F.Cu) (net 87))
(segment (start 161.29 92.075) (end 161.29 81.915) (width 0.35) (layer F.Cu) (net 87))
(segment (start 161.29 81.915) (end 160.655 81.28) (width 0.35) (layer F.Cu) (net 87))
(segment (start 183.515 98.68) (end 183.515 94.615) (width 0.35) (layer F.Cu) (net 87))
(segment (start 181.61 92.71) (end 161.925 92.71) (width 0.35) (layer F.Cu) (net 87))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 139.7 123.19) (end 154.94 123.19) (width 0.35) (layer F.Cu) (net 88))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 175.895 98.68) (end 175.895 111.125) (width 0.35) (layer F.Cu) (net 88))
(segment (start 160.655 117.475) (end 162.560006 115.569994) (width 0.35) (layer F.Cu) (net 88))
(segment (start 160.655 122.555) (end 160.655 117.475) (width 0.35) (layer F.Cu) (net 88))
(segment (start 156.21 123.19) (end 160.02 123.19) (width 0.35) (layer F.Cu) (net 88))
(segment (start 160.02 123.19) (end 160.655 122.555) (width 0.35) (layer F.Cu) (net 88))
(segment (start 154.94 123.19) (end 156.21 123.19) (width 0.35) (layer F.Cu) (net 88))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 139.7 118.11) (end 154.94 118.11) (width 0.35) (layer F.Cu) (net 89))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 177.165 98.68) (end 177.165 111.125) (width 0.35) (layer F.Cu) (net 89))
(segment (start 158.75 118.11) (end 159.385 117.475) (width 0.35) (layer F.Cu) (net 89))
(segment (start 156.21 118.11) (end 158.75 118.11) (width 0.35) (layer F.Cu) (net 89))
(segment (start 159.385 117.475) (end 159.385 115.57) (width 0.35) (layer F.Cu) (net 89))
(segment (start 159.385 115.57) (end 160.655 114.3) (width 0.35) (layer F.Cu) (net 89))
(segment (start 154.94 118.11) (end 156.21 118.11) (width 0.35) (layer F.Cu) (net 89))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 139.7 113.03) (end 154.94 113.03) (width 0.35) (layer F.Cu) (net 90))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 157.41 113.03) (end 156.21 113.03) (width 0.35) (layer F.Cu) (net 90))
(segment (start 160.871366 113.03) (end 156.14 113.03) (width 0.35) (layer F.Cu) (net 90))
(segment (start 177.165 113.03) (end 160.871366 113.03) (width 0.35) (layer F.Cu) (net 90))
(segment (start 178.435 98.68) (end 178.435 111.76) (width 0.35) (layer F.Cu) (net 90))
(segment (start 178.435 111.76) (end 177.165 113.03) (width 0.35) (layer F.Cu) (net 90))
(segment (start 154.94 113.03) (end 156.21 113.03) (width 0.35) (layer F.Cu) (net 90))
(segment (start 154.94 96.52) (end 139.7 96.52) (width 0.35) (layer F.Cu) (net 91))
(segment (start 154.94 96.52) (end 156.21 96.52) (width 0.35) (layer F.Cu) (net 91))
(segment (start 156.21 96.52) (end 179.07 96.52) (width 0.35) (layer F.Cu) (net 91))
(segment (start 179.705 97.155) (end 179.705 98.68) (width 0.35) (layer F.Cu) (net 91))
(segment (start 179.07 96.52) (end 179.705 97.155) (width 0.35) (layer F.Cu) (net 91))
(segment (start 139.7 91.44) (end 154.94 91.44) (width 0.35) (layer F.Cu) (net 92))
(segment (start 180.975 95.885) (end 180.975 98.68) (width 0.35) (layer F.Cu) (net 92))
(segment (start 161.925 95.25) (end 180.34 95.25) (width 0.35) (layer F.Cu) (net 92))
(segment (start 180.34 95.25) (end 180.975 95.885) (width 0.35) (layer F.Cu) (net 92))
(segment (start 154.94 91.44) (end 156.21 91.44) (width 0.35) (layer F.Cu) (net 92))
(segment (start 156.21 91.44) (end 158.115 91.44) (width 0.35) (layer F.Cu) (net 92))
(segment (start 158.115 91.44) (end 158.75 92.075) (width 0.35) (layer F.Cu) (net 92))
(segment (start 158.75 92.075) (end 158.75 94.615) (width 0.35) (layer F.Cu) (net 92))
(segment (start 158.75 94.615) (end 159.385 95.25) (width 0.35) (layer F.Cu) (net 92))
(segment (start 159.385 95.25) (end 161.925 95.25) (width 0.35) (layer F.Cu) (net 92))
(segment (start 154.94 86.36) (end 139.7 86.36) (width 0.35) (layer F.Cu) (net 93))
(segment (start 154.94 86.36) (end 156.21 86.36) (width 0.35) (layer F.Cu) (net 93))
(segment (start 158.75 86.36) (end 156.21 86.36) (width 0.35) (layer F.Cu) (net 93))
(segment (start 159.385 86.36) (end 158.75 86.36) (width 0.35) (layer F.Cu) (net 93))
(segment (start 182.245 95.25) (end 180.975 93.98) (width 0.35) (layer F.Cu) (net 93))
(segment (start 182.245 98.68) (end 182.245 95.25) (width 0.35) (layer F.Cu) (net 93))
(segment (start 180.975 93.98) (end 160.655 93.98) (width 0.35) (layer F.Cu) (net 93))
(segment (start 160.655 93.98) (end 160.02 93.345) (width 0.35) (layer F.Cu) (net 93))
(segment (start 160.02 86.995) (end 159.385 86.36) (width 0.35) (layer F.Cu) (net 93))
(segment (start 160.02 93.345) (end 160.02 86.995) (width 0.35) (layer F.Cu) (net 93))
(segment (start 174.625 98.68) (end 174.625 111.125) (width 0.35) (layer F.Cu) (net 94))
(segment (start 161.925 118.11) (end 163.195 116.84) (width 0.35) (layer F.Cu) (net 94))
(segment (start 161.925 126.365) (end 161.925 118.11) (width 0.35) (layer F.Cu) (net 94))
(segment (start 139.7 128.27) (end 160.02 128.27) (width 0.35) (layer F.Cu) (net 94))
(segment (start 160.02 128.27) (end 161.925 126.365) (width 0.35) (layer F.Cu) (net 94))
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(segment (start 223 81.99) (end 215.19 81.99) (width 0.35) (layer F.Cu) (net 95))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(segment (start 188.595 98.68) (end 188.595 95.25) (width 0.35) (layer F.Cu) (net 95))
(segment (start 198.755 93.98) (end 200.66 92.075) (width 0.35) (layer F.Cu) (net 95))
(segment (start 201.855 81.99) (end 215.19 81.99) (width 0.35) (layer F.Cu) (net 95))
(segment (start 188.595 95.25) (end 189.865 93.98) (width 0.35) (layer F.Cu) (net 95))
(segment (start 189.865 93.98) (end 198.755 93.98) (width 0.35) (layer F.Cu) (net 95))
(segment (start 200.66 83.185) (end 201.855 81.99) (width 0.35) (layer F.Cu) (net 95))
(segment (start 200.66 92.075) (end 200.66 83.185) (width 0.35) (layer F.Cu) (net 95))
(segment (start 201.93 92.71) (end 201.93 85.725) (width 0.35) (layer F.Cu) (net 96))
(segment (start 220.5 84.49) (end 212.09 84.49) (width 0.35) (layer F.Cu) (net 96))
(segment (start 203.235 84.49) (end 212.09 84.49) (width 0.35) (layer F.Cu) (net 96))
(segment (start 212.09 84.49) (end 211.42 84.49) (width 0.35) (layer F.Cu) (net 96))
(segment (start 189.865 98.68) (end 189.865 96.520006) (width 0.35) (layer F.Cu) (net 96))
(segment (start 201.93 85.725) (end 203.2 84.455) (width 0.35) (layer F.Cu) (net 96))
(segment (start 189.865 96.520006) (end 191.135006 95.25) (width 0.35) (layer F.Cu) (net 96))
(segment (start 199.39 95.25) (end 201.93 92.71) (width 0.35) (layer F.Cu) (net 96))
(segment (start 203.2 84.455) (end 203.235 84.49) (width 0.35) (layer F.Cu) (net 96))
(segment (start 191.135006 95.25) (end 199.39 95.25) (width 0.35) (layer F.Cu) (net 96))
(segment (start 191.135 97.155) (end 191.135 98.68) (width 0.35) (layer F.Cu) (net 97))
(segment (start 204.475 86.99) (end 203.2 88.265) (width 0.35) (layer F.Cu) (net 97))
(segment (start 203.2 88.265) (end 203.2 93.345) (width 0.35) (layer F.Cu) (net 97))
(segment (start 203.2 93.345) (end 200.025 96.52) (width 0.35) (layer F.Cu) (net 97))
(segment (start 191.77 96.52) (end 191.135 97.155) (width 0.35) (layer F.Cu) (net 97))
(segment (start 223 86.99) (end 204.475 86.99) (width 0.35) (layer F.Cu) (net 97))
(segment (start 200.025 96.52) (end 191.77 96.52) (width 0.35) (layer F.Cu) (net 97))
start pcb layout
2018-08-26 19:54:32 +00:00
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(zone (net 3) (net_name GNDPWR) (layer B.Cu) (tstamp 5B985757) (hatch edge 0.508)
add ground and power planes
2018-08-28 21:14:49 +00:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 71.12 40.64) (xy 133.35 40.64) (xy 133.35 138.43) (xy 71.12 138.43)
)
)
(filled_polygon
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(xy 131.045423 92.945423) (xy 130.72826 93.420091) (xy 130.616887 93.98) (xy 130.72826 94.539909) (xy 131.045423 95.014577)
(xy 131.397758 95.25) (xy 131.045423 95.485423) (xy 130.72826 95.960091) (xy 130.616887 96.52) (xy 130.72826 97.079909)
(xy 131.045423 97.554577) (xy 131.397758 97.79) (xy 131.045423 98.025423) (xy 130.72826 98.500091) (xy 130.616887 99.06)
(xy 130.72826 99.619909) (xy 131.045423 100.094577) (xy 131.520091 100.41174) (xy 131.938667 100.495) (xy 132.221333 100.495)
(xy 132.639909 100.41174) (xy 133.114577 100.094577) (xy 133.223 99.932311) (xy 133.223 109.617689) (xy 133.114577 109.455423)
(xy 132.639909 109.13826) (xy 132.221333 109.055) (xy 131.938667 109.055) (xy 131.520091 109.13826) (xy 131.045423 109.455423)
(xy 130.72826 109.930091) (xy 130.616887 110.49) (xy 130.72826 111.049909) (xy 131.045423 111.524577) (xy 131.397758 111.76)
(xy 131.045423 111.995423) (xy 130.72826 112.470091) (xy 130.616887 113.03) (xy 130.72826 113.589909) (xy 131.045423 114.064577)
(xy 131.397758 114.3) (xy 131.045423 114.535423) (xy 130.72826 115.010091) (xy 130.616887 115.57) (xy 130.72826 116.129909)
(xy 131.045423 116.604577) (xy 131.397758 116.84) (xy 131.045423 117.075423) (xy 130.72826 117.550091) (xy 130.616887 118.11)
(xy 130.72826 118.669909) (xy 131.045423 119.144577) (xy 131.397758 119.38) (xy 131.045423 119.615423) (xy 130.72826 120.090091)
(xy 130.616887 120.65) (xy 130.72826 121.209909) (xy 131.045423 121.684577) (xy 131.397758 121.92) (xy 131.045423 122.155423)
(xy 130.72826 122.630091) (xy 130.616887 123.19) (xy 130.72826 123.749909) (xy 131.045423 124.224577) (xy 131.397758 124.46)
(xy 131.045423 124.695423) (xy 130.72826 125.170091) (xy 130.616887 125.73) (xy 130.72826 126.289909) (xy 131.045423 126.764577)
(xy 131.397758 127) (xy 131.045423 127.235423) (xy 130.72826 127.710091) (xy 130.616887 128.27) (xy 130.72826 128.829909)
(xy 131.045423 129.304577) (xy 131.520091 129.62174) (xy 131.938667 129.705) (xy 132.221333 129.705) (xy 132.639909 129.62174)
(xy 133.114577 129.304577) (xy 133.223 129.142311) (xy 133.223 138.303) (xy 71.247 138.303) (xy 71.247 112.585431)
(xy 75.235 112.585431) (xy 75.235 113.474569) (xy 75.575259 114.296026) (xy 76.203974 114.924741) (xy 77.025431 115.265)
(xy 77.914569 115.265) (xy 78.736026 114.924741) (xy 79.364741 114.296026) (xy 79.705 113.474569) (xy 79.705 112.585431)
(xy 79.364741 111.763974) (xy 78.736026 111.135259) (xy 77.914569 110.795) (xy 77.025431 110.795) (xy 76.203974 111.135259)
(xy 75.575259 111.763974) (xy 75.235 112.585431) (xy 71.247 112.585431) (xy 71.247 107.745171) (xy 82.422799 107.745171)
(xy 82.45077 108.295448) (xy 82.60754 108.673923) (xy 82.848483 108.741912) (xy 83.640395 107.95) (xy 83.999605 107.95)
(xy 84.791517 108.741912) (xy 85.03246 108.673923) (xy 85.217201 108.154829) (xy 85.18923 107.604552) (xy 85.03246 107.226077)
(xy 84.791517 107.158088) (xy 83.999605 107.95) (xy 83.640395 107.95) (xy 82.848483 107.158088) (xy 82.60754 107.226077)
(xy 82.422799 107.745171) (xy 71.247 107.745171) (xy 71.247 101.155431) (xy 75.235 101.155431) (xy 75.235 102.044569)
(xy 75.575259 102.866026) (xy 76.203974 103.494741) (xy 77.025431 103.835) (xy 77.914569 103.835) (xy 78.736026 103.494741)
(xy 79.364741 102.866026) (xy 79.673755 102.12) (xy 82.42256 102.12) (xy 82.42256 103.62) (xy 82.471843 103.867765)
(xy 82.612191 104.077809) (xy 82.822235 104.218157) (xy 83.014844 104.256469) (xy 82.645853 104.62546) (xy 82.435 105.134506)
(xy 82.435 105.685494) (xy 82.645853 106.19454) (xy 83.03546 106.584147) (xy 83.25093 106.673397) (xy 83.096077 106.73754)
(xy 83.028088 106.978483) (xy 83.82 107.770395) (xy 84.611912 106.978483) (xy 84.543923 106.73754) (xy 84.377342 106.678255)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 84.60454 106.584147) (xy 84.968687 106.22) (xy 85.053612 106.22) (xy 84.962799 106.475171) (xy 84.99077 107.025448)
(xy 85.14754 107.403923) (xy 85.388483 107.471912) (xy 86.180395 106.68) (xy 86.166253 106.665858) (xy 86.345858 106.486253)
(xy 86.36 106.500395) (xy 86.374143 106.486253) (xy 86.553748 106.665858) (xy 86.539605 106.68) (xy 87.331517 107.471912)
(xy 87.57246 107.403923) (xy 87.757201 106.884829) (xy 87.72923 106.334552) (xy 87.681781 106.22) (xy 90.469488 106.22)
(xy 92.715834 108.466347) (xy 92.761023 108.533977) (xy 93.028954 108.713003) (xy 93.265226 108.76) (xy 93.26523 108.76)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 93.344999 108.775867) (xy 93.424769 108.76) (xy 100.885227 108.76) (xy 100.965 108.775868) (xy 101.044773 108.76)
(xy 101.044774 108.76) (xy 101.281046 108.713003) (xy 101.548977 108.533977) (xy 101.594168 108.466345) (xy 102.116347 107.944166)
(xy 102.183977 107.898977) (xy 102.349325 107.651517) (xy 102.363003 107.631047) (xy 102.420293 107.343026) (xy 102.706673 107.151673)
(xy 102.87 106.907237) (xy 103.033327 107.151673) (xy 103.541073 107.490938) (xy 103.988818 107.58) (xy 104.291182 107.58)
(xy 104.738927 107.490938) (xy 105.246673 107.151673) (xy 105.444904 106.855) (xy 107.581289 106.855) (xy 107.326569 107.10972)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 107.169 107.490126) (xy 107.169 107.901874) (xy 107.326569 108.28228) (xy 107.394001 108.349712) (xy 107.394001 108.886223)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 107.394 108.886227) (xy 107.394001 110.156222) (xy 107.394 110.156226) (xy 107.394 110.318565) (xy 107.394001 110.31857)
(xy 107.394 113.710487) (xy 106.979488 114.125) (xy 105.444904 114.125) (xy 105.246673 113.828327) (xy 104.738927 113.489062)
(xy 104.291182 113.4) (xy 103.988818 113.4) (xy 103.541073 113.489062) (xy 103.033327 113.828327) (xy 102.87 114.072763)
(xy 102.706673 113.828327) (xy 102.198927 113.489062) (xy 101.751182 113.4) (xy 101.448818 113.4) (xy 101.001073 113.489062)
(xy 100.557129 113.785696) (xy 100.417809 113.577191) (xy 100.207765 113.436843) (xy 99.96 113.38756) (xy 98.16 113.38756)
(xy 97.912235 113.436843) (xy 97.702191 113.577191) (xy 97.561843 113.787235) (xy 97.51256 114.035) (xy 97.51256 115.835)
(xy 97.551348 116.03) (xy 93.680513 116.03) (xy 88.894168 111.243656) (xy 88.848977 111.176023) (xy 88.581046 110.996997)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 88.344774 110.95) (xy 88.344773 110.95) (xy 88.265 110.934132) (xy 88.185227 110.95) (xy 87.508687 110.95)
(xy 87.14454 110.585853) (xy 86.91313 110.49) (xy 87.14454 110.394147) (xy 87.508687 110.03) (xy 89.834488 110.03)
(xy 92.715834 112.911347) (xy 92.761023 112.978977) (xy 93.028954 113.158003) (xy 93.265226 113.205) (xy 93.344999 113.220868)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 93.424772 113.205) (xy 100.885227 113.205) (xy 100.965 113.220868) (xy 101.044773 113.205) (xy 101.044774 113.205)
(xy 101.281046 113.158003) (xy 101.548977 112.978977) (xy 101.594168 112.911345) (xy 102.116347 112.389166) (xy 102.183977 112.343977)
(xy 102.271673 112.21273) (xy 102.363003 112.076047) (xy 102.420293 111.788026) (xy 102.706673 111.596673) (xy 102.87 111.352237)
(xy 103.033327 111.596673) (xy 103.541073 111.935938) (xy 103.988818 112.025) (xy 104.291182 112.025) (xy 104.738927 111.935938)
(xy 105.246673 111.596673) (xy 105.585938 111.088927) (xy 105.705072 110.49) (xy 105.585938 109.891073) (xy 105.246673 109.383327)
(xy 104.738927 109.044062) (xy 104.291182 108.955) (xy 103.988818 108.955) (xy 103.541073 109.044062) (xy 103.033327 109.383327)
(xy 102.87 109.627763) (xy 102.706673 109.383327) (xy 102.198927 109.044062) (xy 101.751182 108.955) (xy 101.448818 108.955)
(xy 101.001073 109.044062) (xy 100.557129 109.340696) (xy 100.417809 109.132191) (xy 100.207765 108.991843) (xy 99.96 108.94256)
(xy 98.16 108.94256) (xy 97.912235 108.991843) (xy 97.702191 109.132191) (xy 97.561843 109.342235) (xy 97.51256 109.59)
(xy 97.51256 111.39) (xy 97.551348 111.585) (xy 93.680513 111.585) (xy 90.799168 108.703656) (xy 90.753977 108.636023)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 90.486046 108.456997) (xy 90.249774 108.41) (xy 90.249773 108.41) (xy 90.17 108.394132) (xy 90.090227 108.41)
(xy 87.508687 108.41) (xy 87.14454 108.045853) (xy 86.92907 107.956603) (xy 87.083923 107.89246) (xy 87.151912 107.651517)
(xy 86.36 106.859605) (xy 85.568088 107.651517) (xy 85.636077 107.89246) (xy 85.802658 107.951745) (xy 85.57546 108.045853)
(xy 85.185853 108.43546) (xy 84.975 108.944506) (xy 84.975 109.495494) (xy 85.185853 110.00454) (xy 85.57546 110.394147)
(xy 85.80687 110.49) (xy 85.57546 110.585853) (xy 85.185853 110.97546) (xy 84.975 111.484506) (xy 84.975 112.035494)
(xy 85.185853 112.54454) (xy 85.57546 112.934147) (xy 86.084506 113.145) (xy 86.635494 113.145) (xy 87.14454 112.934147)
(xy 87.508687 112.57) (xy 87.929488 112.57) (xy 92.715834 117.356347) (xy 92.761023 117.423977) (xy 93.028954 117.603003)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 93.265226 117.65) (xy 93.265227 117.65) (xy 93.345 117.665868) (xy 93.424773 117.65) (xy 100.885227 117.65)
(xy 100.965 117.665868) (xy 101.044773 117.65) (xy 101.044774 117.65) (xy 101.281046 117.603003) (xy 101.548977 117.423977)
(xy 101.594168 117.356345) (xy 102.116347 116.834166) (xy 102.183977 116.788977) (xy 102.278145 116.648045) (xy 102.363003 116.521047)
(xy 102.420293 116.233026) (xy 102.706673 116.041673) (xy 102.87 115.797237) (xy 103.033327 116.041673) (xy 103.541073 116.380938)
(xy 103.988818 116.47) (xy 104.291182 116.47) (xy 104.738927 116.380938) (xy 105.246673 116.041673) (xy 105.444904 115.745)
(xy 107.235227 115.745) (xy 107.315 115.760868) (xy 107.394773 115.745) (xy 107.394774 115.745) (xy 107.631046 115.698003)
(xy 107.898977 115.518977) (xy 107.944168 115.451344) (xy 108.720347 114.675166) (xy 108.787977 114.629977) (xy 108.967003 114.362046)
(xy 109.014 114.125774) (xy 109.014 114.125773) (xy 109.029868 114.046) (xy 109.014 113.966227) (xy 109.014 108.349711)
(xy 109.081431 108.28228) (xy 109.239 107.901874) (xy 109.239 107.490126) (xy 109.081431 107.10972) (xy 108.826711 106.855)
(xy 112.661289 106.855) (xy 112.406569 107.10972) (xy 112.249 107.490126) (xy 112.249 107.901874) (xy 112.406569 108.28228)
(xy 112.474001 108.349712) (xy 112.474 115.996487) (xy 109.900488 118.57) (xy 105.444904 118.57) (xy 105.246673 118.273327)
(xy 104.738927 117.934062) (xy 104.291182 117.845) (xy 103.988818 117.845) (xy 103.541073 117.934062) (xy 103.033327 118.273327)
(xy 102.87 118.517763) (xy 102.706673 118.273327) (xy 102.198927 117.934062) (xy 101.751182 117.845) (xy 101.448818 117.845)
(xy 101.001073 117.934062) (xy 100.557129 118.230696) (xy 100.417809 118.022191) (xy 100.207765 117.881843) (xy 99.96 117.83256)
(xy 98.16 117.83256) (xy 97.912235 117.881843) (xy 97.702191 118.022191) (xy 97.561843 118.232235) (xy 97.51256 118.48)
(xy 97.51256 120.28) (xy 97.551348 120.475) (xy 94.315513 120.475) (xy 90.164168 116.323656) (xy 90.118977 116.256023)
(xy 89.851046 116.076997) (xy 89.614774 116.03) (xy 89.614773 116.03) (xy 89.535 116.014132) (xy 89.455227 116.03)
(xy 86.060513 116.03) (xy 84.63 114.599488) (xy 84.63 111.638687) (xy 84.994147 111.27454) (xy 85.205 110.765494)
(xy 85.205 110.214506) (xy 84.994147 109.70546) (xy 84.60454 109.315853) (xy 84.38907 109.226603) (xy 84.543923 109.16246)
(xy 84.611912 108.921517) (xy 83.82 108.129605) (xy 83.028088 108.921517) (xy 83.096077 109.16246) (xy 83.262658 109.221745)
(xy 83.03546 109.315853) (xy 82.645853 109.70546) (xy 82.435 110.214506) (xy 82.435 110.765494) (xy 82.645853 111.27454)
(xy 83.01 111.638687) (xy 83.010001 114.855222) (xy 82.994132 114.935) (xy 83.056998 115.251046) (xy 83.236024 115.518977)
(xy 83.303653 115.564165) (xy 85.095834 117.356347) (xy 85.141023 117.423977) (xy 85.408954 117.603003) (xy 85.645226 117.65)
(xy 85.645227 117.65) (xy 85.725 117.665868) (xy 85.804773 117.65) (xy 89.199488 117.65) (xy 93.350834 121.801347)
(xy 93.396023 121.868977) (xy 93.663954 122.048003) (xy 93.900226 122.095) (xy 93.90023 122.095) (xy 93.979999 122.110867)
(xy 94.059769 122.095) (xy 100.885227 122.095) (xy 100.965 122.110868) (xy 101.044773 122.095) (xy 101.044774 122.095)
(xy 101.281046 122.048003) (xy 101.548977 121.868977) (xy 101.594168 121.801345) (xy 102.116347 121.279166) (xy 102.183977 121.233977)
(xy 102.351158 120.983774) (xy 102.363003 120.966047) (xy 102.420293 120.678026) (xy 102.706673 120.486673) (xy 102.87 120.242237)
(xy 103.033327 120.486673) (xy 103.541073 120.825938) (xy 103.988818 120.915) (xy 104.291182 120.915) (xy 104.738927 120.825938)
(xy 105.246673 120.486673) (xy 105.444904 120.19) (xy 110.156227 120.19) (xy 110.236 120.205868) (xy 110.315773 120.19)
(xy 110.315774 120.19) (xy 110.552046 120.143003) (xy 110.819977 119.963977) (xy 110.865168 119.896344) (xy 113.800347 116.961166)
(xy 113.867977 116.915977) (xy 114.047003 116.648046) (xy 114.094 116.411774) (xy 114.094 116.411773) (xy 114.109868 116.332)
(xy 114.094 116.252227) (xy 114.094 108.349711) (xy 114.161431 108.28228) (xy 114.319 107.901874) (xy 114.319 107.490126)
(xy 114.210379 107.227892) (xy 115.014001 108.031514) (xy 115.014 115.678289) (xy 114.946569 115.74572) (xy 114.789 116.126126)
(xy 114.789 116.537874) (xy 114.946569 116.91828) (xy 115.23772 117.209431) (xy 115.618126 117.367) (xy 116.029874 117.367)
(xy 116.41028 117.209431) (xy 116.701431 116.91828) (xy 116.859 116.537874) (xy 116.859 116.126126) (xy 116.701431 115.74572)
(xy 116.634 115.678289) (xy 116.634 107.775774) (xy 116.649868 107.696) (xy 116.587003 107.379953) (xy 116.495673 107.24327)
(xy 116.407977 107.112023) (xy 116.340347 107.066834) (xy 114.802168 105.528656) (xy 114.756977 105.461023) (xy 114.489046 105.281997)
(xy 114.252774 105.235) (xy 114.252773 105.235) (xy 114.173 105.219132) (xy 114.093227 105.235) (xy 105.444904 105.235)
(xy 105.246673 104.938327) (xy 104.738927 104.599062) (xy 104.291182 104.51) (xy 103.988818 104.51) (xy 103.541073 104.599062)
(xy 103.033327 104.938327) (xy 102.87 105.182763) (xy 102.706673 104.938327) (xy 102.198927 104.599062) (xy 101.751182 104.51)
(xy 101.448818 104.51) (xy 101.001073 104.599062) (xy 100.557129 104.895696) (xy 100.417809 104.687191) (xy 100.207765 104.546843)
(xy 99.96 104.49756) (xy 98.16 104.49756) (xy 97.912235 104.546843) (xy 97.702191 104.687191) (xy 97.561843 104.897235)
(xy 97.51256 105.145) (xy 97.51256 106.945) (xy 97.551348 107.14) (xy 93.680513 107.14) (xy 91.434168 104.893656)
(xy 91.388977 104.826023) (xy 91.121046 104.646997) (xy 90.884774 104.6) (xy 90.884773 104.6) (xy 90.805 104.584132)
(xy 90.725227 104.6) (xy 90.220512 104.6) (xy 90.505513 104.315) (xy 100.885227 104.315) (xy 100.965 104.330868)
(xy 101.044773 104.315) (xy 101.044774 104.315) (xy 101.281046 104.268003) (xy 101.548977 104.088977) (xy 101.594168 104.021345)
(xy 102.116347 103.499166) (xy 102.183977 103.453977) (xy 102.323501 103.245165) (xy 102.363003 103.186047) (xy 102.420293 102.898026)
(xy 102.706673 102.706673) (xy 102.87 102.462237) (xy 103.033327 102.706673) (xy 103.541073 103.045938) (xy 103.988818 103.135)
(xy 104.291182 103.135) (xy 104.738927 103.045938) (xy 105.246673 102.706673) (xy 105.444904 102.41) (xy 114.472488 102.41)
(xy 117.046001 104.983514) (xy 117.046 120.250289) (xy 116.978569 120.31772) (xy 116.821 120.698126) (xy 116.821 121.109874)
(xy 116.978569 121.49028) (xy 117.26972 121.781431) (xy 117.650126 121.939) (xy 118.061874 121.939) (xy 118.44228 121.781431)
(xy 118.57 121.653711) (xy 118.57 124.314289) (xy 118.502569 124.38172) (xy 118.345 124.762126) (xy 118.345 125.173874)
(xy 118.502569 125.55428) (xy 118.79372 125.845431) (xy 119.174126 126.003) (xy 119.585874 126.003) (xy 119.96628 125.845431)
(xy 120.257431 125.55428) (xy 120.415 125.173874) (xy 120.415 124.762126) (xy 120.257431 124.38172) (xy 120.19 124.314289)
(xy 120.19 102.695772) (xy 120.205868 102.615999) (xy 120.155544 102.363003) (xy 120.143003 102.299954) (xy 119.963977 102.032023)
(xy 119.896347 101.986834) (xy 114.548168 96.638656) (xy 114.502977 96.571023) (xy 114.235046 96.391997) (xy 113.998774 96.345)
(xy 113.998773 96.345) (xy 113.919 96.329132) (xy 113.839227 96.345) (xy 105.444904 96.345) (xy 105.246673 96.048327)
(xy 104.738927 95.709062) (xy 104.291182 95.62) (xy 103.988818 95.62) (xy 103.541073 95.709062) (xy 103.033327 96.048327)
(xy 102.87 96.292763) (xy 102.706673 96.048327) (xy 102.198927 95.709062) (xy 101.751182 95.62) (xy 101.448818 95.62)
(xy 101.001073 95.709062) (xy 100.557129 96.005696) (xy 100.417809 95.797191) (xy 100.207765 95.656843) (xy 99.96 95.60756)
(xy 98.16 95.60756) (xy 97.912235 95.656843) (xy 97.702191 95.797191) (xy 97.561843 96.007235) (xy 97.51256 96.255)
(xy 97.51256 98.055) (xy 97.551348 98.25) (xy 85.169772 98.25) (xy 85.089999 98.234132) (xy 85.010226 98.25)
(xy 84.773954 98.296997) (xy 84.506023 98.476023) (xy 84.460834 98.543653) (xy 83.303654 99.700834) (xy 83.236024 99.746023)
(xy 83.190835 99.813653) (xy 83.056998 100.013954) (xy 82.994132 100.33) (xy 83.010001 100.409778) (xy 83.010001 101.484495)
(xy 82.822235 101.521843) (xy 82.612191 101.662191) (xy 82.471843 101.872235) (xy 82.42256 102.12) (xy 79.673755 102.12)
(xy 79.705 102.044569) (xy 79.705 101.155431) (xy 79.364741 100.333974) (xy 78.736026 99.705259) (xy 77.914569 99.365)
(xy 77.025431 99.365) (xy 76.203974 99.705259) (xy 75.575259 100.333974) (xy 75.235 101.155431) (xy 71.247 101.155431)
(xy 71.247 78.295431) (xy 75.235 78.295431) (xy 75.235 79.184569) (xy 75.575259 80.006026) (xy 76.203974 80.634741)
(xy 77.025431 80.975) (xy 77.914569 80.975) (xy 78.736026 80.634741) (xy 79.364741 80.006026) (xy 79.705 79.184569)
(xy 79.705 78.295431) (xy 79.364741 77.473974) (xy 78.736026 76.845259) (xy 77.914569 76.505) (xy 77.025431 76.505)
(xy 76.203974 76.845259) (xy 75.575259 77.473974) (xy 75.235 78.295431) (xy 71.247 78.295431) (xy 71.247 75.924506)
(xy 82.435 75.924506) (xy 82.435 76.475494) (xy 82.645853 76.98454) (xy 83.01 77.348687) (xy 83.010001 78.660222)
(xy 82.994132 78.74) (xy 83.044457 78.992998) (xy 83.056998 79.056046) (xy 83.236024 79.323977) (xy 83.303653 79.369165)
(xy 83.825834 79.891347) (xy 83.871023 79.958977) (xy 84.00227 80.046673) (xy 84.138953 80.138003) (xy 84.455 80.200868)
(xy 84.534774 80.185) (xy 91.104488 80.185) (xy 91.265 80.345513) (xy 91.265001 83.105222) (xy 91.249132 83.185)
(xy 91.311998 83.501046) (xy 91.491024 83.768977) (xy 91.558653 83.814165) (xy 92.715834 84.971347) (xy 92.761023 85.038977)
(xy 93.028954 85.218003) (xy 93.265226 85.265) (xy 93.344999 85.280868) (xy 93.424772 85.265) (xy 95.549488 85.265)
(xy 95.710001 85.425513) (xy 95.71 86.915226) (xy 95.694132 86.995) (xy 95.71 87.074773) (xy 95.756997 87.311045)
(xy 95.936023 87.578977) (xy 96.003655 87.624168) (xy 96.525834 88.146347) (xy 96.571023 88.213977) (xy 96.638652 88.259165)
(xy 96.838953 88.393003) (xy 97.155 88.455868) (xy 97.234774 88.44) (xy 100.885227 88.44) (xy 100.965 88.455868)
(xy 101.044773 88.44) (xy 101.044774 88.44) (xy 101.281046 88.393003) (xy 101.548977 88.213977) (xy 101.594168 88.146345)
(xy 102.116347 87.624166) (xy 102.183977 87.578977) (xy 102.271673 87.44773) (xy 102.363003 87.311047) (xy 102.420293 87.023026)
(xy 102.706673 86.831673) (xy 102.87 86.587237) (xy 103.033327 86.831673) (xy 103.541073 87.170938) (xy 103.988818 87.26)
(xy 104.291182 87.26) (xy 104.738927 87.170938) (xy 105.246673 86.831673) (xy 105.444904 86.535) (xy 112.823227 86.535)
(xy 112.903 86.550868) (xy 112.982773 86.535) (xy 112.982774 86.535) (xy 113.219046 86.488003) (xy 113.486977 86.308977)
(xy 113.532168 86.241344) (xy 115.324347 84.449166) (xy 115.391977 84.403977) (xy 115.571003 84.136046) (xy 115.618 83.899774)
(xy 115.618 83.899773) (xy 115.633868 83.82) (xy 115.618 83.740227) (xy 115.618 66.693711) (xy 115.685431 66.62628)
(xy 115.843 66.245874) (xy 115.843 65.834126) (xy 115.685431 65.45372) (xy 115.39428 65.162569) (xy 115.013874 65.005)
(xy 114.602126 65.005) (xy 114.22172 65.162569) (xy 113.930569 65.45372) (xy 113.773 65.834126) (xy 113.773 66.245874)
(xy 113.930569 66.62628) (xy 113.998001 66.693712) (xy 113.998 75.104226) (xy 113.998 75.104227) (xy 113.998001 83.484486)
(xy 112.567488 84.915) (xy 105.444904 84.915) (xy 105.246673 84.618327) (xy 104.738927 84.279062) (xy 104.291182 84.19)
(xy 103.988818 84.19) (xy 103.541073 84.279062) (xy 103.033327 84.618327) (xy 102.87 84.862763) (xy 102.706673 84.618327)
(xy 102.198927 84.279062) (xy 101.751182 84.19) (xy 101.448818 84.19) (xy 101.001073 84.279062) (xy 100.557129 84.575696)
(xy 100.417809 84.367191) (xy 100.207765 84.226843) (xy 99.96 84.17756) (xy 98.16 84.17756) (xy 97.912235 84.226843)
(xy 97.702191 84.367191) (xy 97.561843 84.577235) (xy 97.51256 84.825) (xy 97.51256 86.625) (xy 97.551348 86.82)
(xy 97.490513 86.82) (xy 97.33 86.659488) (xy 97.33 85.169774) (xy 97.345868 85.09) (xy 97.283003 84.773953)
(xy 97.149165 84.573652) (xy 97.103977 84.506023) (xy 97.036347 84.460834) (xy 96.570512 83.995) (xy 100.885227 83.995)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 100.965 84.010868) (xy 101.044773 83.995) (xy 101.044774 83.995) (xy 101.281046 83.948003) (xy 101.548977 83.768977)
(xy 101.594168 83.701345) (xy 102.116347 83.179166) (xy 102.183977 83.133977) (xy 102.277419 82.994132) (xy 102.363003 82.866047)
(xy 102.420293 82.578026) (xy 102.706673 82.386673) (xy 102.87 82.142237) (xy 103.033327 82.386673) (xy 103.541073 82.725938)
(xy 103.988818 82.815) (xy 104.291182 82.815) (xy 104.738927 82.725938) (xy 105.246673 82.386673) (xy 105.444904 82.09)
(xy 109.140227 82.09) (xy 109.22 82.105868) (xy 109.299773 82.09) (xy 109.299774 82.09) (xy 109.536046 82.043003)
(xy 109.803977 81.863977) (xy 109.849168 81.796344) (xy 111.260347 80.385166) (xy 111.327977 80.339977) (xy 111.507003 80.072046)
(xy 111.554 79.835774) (xy 111.554 79.83577) (xy 111.569867 79.756001) (xy 111.554 79.676232) (xy 111.554 66.693711)
(xy 111.621431 66.62628) (xy 111.779 66.245874) (xy 111.779 65.834126) (xy 111.621431 65.45372) (xy 111.33028 65.162569)
(xy 110.949874 65.005) (xy 110.538126 65.005) (xy 110.15772 65.162569) (xy 109.866569 65.45372) (xy 109.709 65.834126)
(xy 109.709 66.245874) (xy 109.866569 66.62628) (xy 109.934001 66.693712) (xy 109.934 79.420487) (xy 108.884488 80.47)
(xy 105.444904 80.47) (xy 105.246673 80.173327) (xy 104.738927 79.834062) (xy 104.291182 79.745) (xy 103.988818 79.745)
(xy 103.541073 79.834062) (xy 103.033327 80.173327) (xy 102.87 80.417763) (xy 102.706673 80.173327) (xy 102.198927 79.834062)
(xy 101.751182 79.745) (xy 101.448818 79.745) (xy 101.001073 79.834062) (xy 100.557129 80.130696) (xy 100.417809 79.922191)
(xy 100.207765 79.781843) (xy 99.96 79.73256) (xy 98.16 79.73256) (xy 97.912235 79.781843) (xy 97.702191 79.922191)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 97.561843 80.132235) (xy 97.51256 80.38) (xy 97.51256 82.18) (xy 97.551348 82.375) (xy 94.315513 82.375)
(xy 94.155 82.214488) (xy 94.155 78.790512) (xy 94.620834 79.256347) (xy 94.666023 79.323977) (xy 94.79727 79.411673)
(xy 94.933953 79.503003) (xy 95.25 79.565868) (xy 95.329774 79.55) (xy 100.885227 79.55) (xy 100.965 79.565868)
(xy 101.044773 79.55) (xy 101.044774 79.55) (xy 101.281046 79.503003) (xy 101.548977 79.323977) (xy 101.594168 79.256345)
(xy 102.116348 78.734165) (xy 102.183977 78.688977) (xy 102.277419 78.549132) (xy 102.363003 78.421047) (xy 102.420293 78.133026)
(xy 102.706673 77.941673) (xy 102.87 77.697237) (xy 103.033327 77.941673) (xy 103.541073 78.280938) (xy 103.988818 78.37)
(xy 104.291182 78.37) (xy 104.738927 78.280938) (xy 105.246673 77.941673) (xy 105.585938 77.433927) (xy 105.705072 76.835)
(xy 105.585938 76.236073) (xy 105.246673 75.728327) (xy 104.738927 75.389062) (xy 104.291182 75.3) (xy 103.988818 75.3)
(xy 103.541073 75.389062) (xy 103.033327 75.728327) (xy 102.87 75.972763) (xy 102.706673 75.728327) (xy 102.198927 75.389062)
(xy 101.751182 75.3) (xy 101.448818 75.3) (xy 101.001073 75.389062) (xy 100.557129 75.685696) (xy 100.417809 75.477191)
(xy 100.207765 75.336843) (xy 99.96 75.28756) (xy 98.16 75.28756) (xy 97.912235 75.336843) (xy 97.702191 75.477191)
(xy 97.561843 75.687235) (xy 97.51256 75.935) (xy 97.51256 77.735) (xy 97.551348 77.93) (xy 95.585513 77.93)
(xy 95.425 77.769488) (xy 95.425 75.644774) (xy 95.440868 75.565) (xy 95.378003 75.248953) (xy 95.250413 75.058002)
(xy 95.198977 74.981023) (xy 95.131347 74.935834) (xy 94.609168 74.413655) (xy 94.563977 74.346023) (xy 94.296046 74.166997)
(xy 94.059774 74.12) (xy 94.059773 74.12) (xy 93.98 74.104132) (xy 93.900227 74.12) (xy 87.508687 74.12)
(xy 87.14454 73.755853) (xy 86.92907 73.666603) (xy 87.083923 73.60246) (xy 87.151912 73.361517) (xy 86.36 72.569605)
(xy 85.568088 73.361517) (xy 85.636077 73.60246) (xy 85.802658 73.661745) (xy 85.57546 73.755853) (xy 85.185853 74.14546)
(xy 84.975 74.654506) (xy 84.975 75.205494) (xy 85.185853 75.71454) (xy 85.57546 76.104147) (xy 85.80687 76.2)
(xy 85.57546 76.295853) (xy 85.185853 76.68546) (xy 84.975 77.194506) (xy 84.975 77.745494) (xy 85.185853 78.25454)
(xy 85.496313 78.565) (xy 84.790513 78.565) (xy 84.63 78.404488) (xy 84.63 77.348687) (xy 84.994147 76.98454)
(xy 85.205 76.475494) (xy 85.205 75.924506) (xy 84.994147 75.41546) (xy 84.60454 75.025853) (xy 84.38907 74.936603)
(xy 84.543923 74.87246) (xy 84.611912 74.631517) (xy 83.82 73.839605) (xy 83.028088 74.631517) (xy 83.096077 74.87246)
add ground and power planes
2018-08-28 21:14:49 +00:00
(xy 83.262658 74.931745) (xy 83.03546 75.025853) (xy 82.645853 75.41546) (xy 82.435 75.924506) (xy 71.247 75.924506)
(xy 71.247 73.455171) (xy 82.422799 73.455171) (xy 82.45077 74.005448) (xy 82.60754 74.383923) (xy 82.848483 74.451912)
(xy 83.640395 73.66) (xy 83.999605 73.66) (xy 84.791517 74.451912) (xy 85.03246 74.383923) (xy 85.217201 73.864829)
(xy 85.18923 73.314552) (xy 85.03246 72.936077) (xy 84.791517 72.868088) (xy 83.999605 73.66) (xy 83.640395 73.66)
(xy 82.848483 72.868088) (xy 82.60754 72.936077) (xy 82.422799 73.455171) (xy 71.247 73.455171) (xy 71.247 66.865431)
(xy 75.235 66.865431) (xy 75.235 67.754569) (xy 75.575259 68.576026) (xy 76.203974 69.204741) (xy 77.025431 69.545)
(xy 77.914569 69.545) (xy 78.736026 69.204741) (xy 79.364741 68.576026) (xy 79.673755 67.83) (xy 82.42256 67.83)
(xy 82.42256 69.33) (xy 82.471843 69.577765) (xy 82.612191 69.787809) (xy 82.822235 69.928157) (xy 83.014844 69.966469)
(xy 82.645853 70.33546) (xy 82.435 70.844506) (xy 82.435 71.395494) (xy 82.645853 71.90454) (xy 83.03546 72.294147)
(xy 83.25093 72.383397) (xy 83.096077 72.44754) (xy 83.028088 72.688483) (xy 83.82 73.480395) (xy 84.611912 72.688483)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 84.543923 72.44754) (xy 84.377342 72.388255) (xy 84.60454 72.294147) (xy 84.968687 71.93) (xy 85.053612 71.93)
(xy 84.962799 72.185171) (xy 84.99077 72.735448) (xy 85.14754 73.113923) (xy 85.388483 73.181912) (xy 86.180395 72.39)
(xy 86.166253 72.375858) (xy 86.345858 72.196253) (xy 86.36 72.210395) (xy 86.374143 72.196253) (xy 86.553748 72.375858)
(xy 86.539605 72.39) (xy 87.331517 73.181912) (xy 87.57246 73.113923) (xy 87.757201 72.594829) (xy 87.72923 72.044552)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 87.681781 71.93) (xy 94.914488 71.93) (xy 95.075001 72.090513) (xy 95.075 73.580226) (xy 95.059132 73.66)
(xy 95.075 73.739773) (xy 95.121997 73.976045) (xy 95.301023 74.243977) (xy 95.368655 74.289168) (xy 95.890834 74.811347)
(xy 95.936023 74.878977) (xy 96.06727 74.966673) (xy 96.203953 75.058003) (xy 96.52 75.120868) (xy 96.599774 75.105)
(xy 100.885227 75.105) (xy 100.965 75.120868) (xy 101.044773 75.105) (xy 101.044774 75.105) (xy 101.281046 75.058003)
(xy 101.548977 74.878977) (xy 101.594168 74.811345) (xy 102.116347 74.289166) (xy 102.183977 74.243977) (xy 102.277419 74.104132)
(xy 102.363003 73.976047) (xy 102.420293 73.688026) (xy 102.706673 73.496673) (xy 102.87 73.252237) (xy 103.033327 73.496673)
(xy 103.541073 73.835938) (xy 103.988818 73.925) (xy 104.291182 73.925) (xy 104.738927 73.835938) (xy 105.246673 73.496673)
(xy 105.585938 72.988927) (xy 105.705072 72.39) (xy 105.585938 71.791073) (xy 105.246673 71.283327) (xy 104.738927 70.944062)
(xy 104.291182 70.855) (xy 103.988818 70.855) (xy 103.541073 70.944062) (xy 103.033327 71.283327) (xy 102.87 71.527763)
(xy 102.706673 71.283327) (xy 102.198927 70.944062) (xy 101.751182 70.855) (xy 101.448818 70.855) (xy 101.001073 70.944062)
(xy 100.557129 71.240696) (xy 100.417809 71.032191) (xy 100.207765 70.891843) (xy 99.96 70.84256) (xy 98.16 70.84256)
(xy 97.912235 70.891843) (xy 97.702191 71.032191) (xy 97.561843 71.242235) (xy 97.51256 71.49) (xy 97.51256 73.29)
(xy 97.551348 73.485) (xy 96.855513 73.485) (xy 96.695 73.324488) (xy 96.695 71.834774) (xy 96.710868 71.755)
(xy 96.648003 71.438953) (xy 96.514165 71.238652) (xy 96.468977 71.171023) (xy 96.401347 71.125834) (xy 95.935512 70.66)
(xy 100.885227 70.66) (xy 100.965 70.675868) (xy 101.044773 70.66) (xy 101.044774 70.66) (xy 101.281046 70.613003)
(xy 101.548977 70.433977) (xy 101.594168 70.366345) (xy 102.116347 69.844166) (xy 102.183977 69.798977) (xy 102.271673 69.66773)
(xy 102.363003 69.531047) (xy 102.420293 69.243026) (xy 102.706673 69.051673) (xy 102.87 68.807237) (xy 103.033327 69.051673)
(xy 103.541073 69.390938) (xy 103.988818 69.48) (xy 104.291182 69.48) (xy 104.738927 69.390938) (xy 105.246673 69.051673)
(xy 105.585938 68.543927) (xy 105.705072 67.945) (xy 105.585938 67.346073) (xy 105.246673 66.838327) (xy 104.738927 66.499062)
(xy 104.291182 66.41) (xy 103.988818 66.41) (xy 103.541073 66.499062) (xy 103.033327 66.838327) (xy 102.87 67.082763)
(xy 102.706673 66.838327) (xy 102.198927 66.499062) (xy 101.751182 66.41) (xy 101.448818 66.41) (xy 101.001073 66.499062)
(xy 100.557129 66.795696) (xy 100.417809 66.587191) (xy 100.207765 66.446843) (xy 99.96 66.39756) (xy 98.16 66.39756)
(xy 97.912235 66.446843) (xy 97.702191 66.587191) (xy 97.561843 66.797235) (xy 97.51256 67.045) (xy 97.51256 68.845)
(xy 97.551348 69.04) (xy 87.508687 69.04) (xy 87.14454 68.675853) (xy 86.635494 68.465) (xy 86.084506 68.465)
(xy 85.57546 68.675853) (xy 85.21744 69.033873) (xy 85.21744 67.83) (xy 85.168157 67.582235) (xy 85.027809 67.372191)
(xy 84.817765 67.231843) (xy 84.63 67.194495) (xy 84.63 67.010512) (xy 85.425513 66.215) (xy 100.885227 66.215)
(xy 100.965 66.230868) (xy 101.044773 66.215) (xy 101.044774 66.215) (xy 101.281046 66.168003) (xy 101.548977 65.988977)
(xy 101.594168 65.921345) (xy 102.116347 65.399166) (xy 102.183977 65.353977) (xy 102.319602 65.151) (xy 102.363003 65.086047)
(xy 102.420293 64.798026) (xy 102.706673 64.606673) (xy 102.87 64.362237) (xy 103.033327 64.606673) (xy 103.541073 64.945938)
(xy 103.988818 65.035) (xy 104.291182 65.035) (xy 104.738927 64.945938) (xy 105.246673 64.606673) (xy 105.444904 64.31)
(xy 115.869488 64.31) (xy 117.046001 65.486514) (xy 117.046 80.626289) (xy 116.978569 80.69372) (xy 116.821 81.074126)
(xy 116.821 81.485874) (xy 116.978569 81.86628) (xy 117.26972 82.157431) (xy 117.650126 82.315) (xy 118.061874 82.315)
(xy 118.44228 82.157431) (xy 118.733431 81.86628) (xy 118.891 81.485874) (xy 118.891 81.074126) (xy 118.733431 80.69372)
(xy 118.666 80.626289) (xy 118.666 76.441711) (xy 118.79372 76.569431) (xy 119.174126 76.727) (xy 119.585874 76.727)
(xy 119.96628 76.569431) (xy 120.257431 76.27828) (xy 120.415 75.897874) (xy 120.415 75.486126) (xy 120.257431 75.10572)
(xy 120.19 75.038289) (xy 120.19 70.406126) (xy 120.377 70.406126) (xy 120.377 70.817874) (xy 120.534569 71.19828)
(xy 120.82572 71.489431) (xy 121.206126 71.647) (xy 121.617874 71.647) (xy 121.99828 71.489431) (xy 122.289431 71.19828)
(xy 122.447 70.817874) (xy 122.447 70.722512) (xy 124.062513 69.107) (xy 124.157874 69.107) (xy 124.53828 68.949431)
(xy 124.829431 68.65828) (xy 124.987 68.277874) (xy 124.987 67.866126) (xy 124.829431 67.48572) (xy 124.53828 67.194569)
(xy 124.157874 67.037) (xy 123.746126 67.037) (xy 123.36572 67.194569) (xy 123.074569 67.48572) (xy 122.917 67.866126)
(xy 122.917 67.961487) (xy 121.301488 69.577) (xy 121.206126 69.577) (xy 120.82572 69.734569) (xy 120.534569 70.02572)
(xy 120.377 70.406126) (xy 120.19 70.406126) (xy 120.19 62.629711) (xy 120.257431 62.56228) (xy 120.415 62.181874)
(xy 120.415 61.770126) (xy 120.257431 61.38972) (xy 119.96628 61.098569) (xy 119.585874 60.941) (xy 119.174126 60.941)
(xy 118.79372 61.098569) (xy 118.502569 61.38972) (xy 118.345 61.770126) (xy 118.345 62.181874) (xy 118.502569 62.56228)
(xy 118.570001 62.629712) (xy 118.57 64.761616) (xy 118.493927 64.647765) (xy 118.439977 64.567023) (xy 118.372347 64.521834)
(xy 116.834168 62.983656) (xy 116.788977 62.916023) (xy 116.521046 62.736997) (xy 116.284774 62.69) (xy 116.284773 62.69)
(xy 116.205 62.674132) (xy 116.125227 62.69) (xy 105.444904 62.69) (xy 105.246673 62.393327) (xy 104.738927 62.054062)
(xy 104.291182 61.965) (xy 103.988818 61.965) (xy 103.541073 62.054062) (xy 103.033327 62.393327) (xy 102.87 62.637763)
(xy 102.706673 62.393327) (xy 102.198927 62.054062) (xy 101.751182 61.965) (xy 101.448818 61.965) (xy 101.001073 62.054062)
(xy 100.557129 62.350696) (xy 100.417809 62.142191) (xy 100.207765 62.001843) (xy 99.96 61.95256) (xy 98.16 61.95256)
(xy 97.912235 62.001843) (xy 97.702191 62.142191) (xy 97.561843 62.352235) (xy 97.51256 62.6) (xy 97.51256 64.4)
(xy 97.551348 64.595) (xy 85.169772 64.595) (xy 85.089999 64.579132) (xy 85.010226 64.595) (xy 84.773954 64.641997)
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add ground and power planes
2018-08-28 21:14:49 +00:00
)
)
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(zone (net 3) (net_name GNDPWR) (layer F.Cu) (tstamp 5B985754) (hatch edge 0.508)
add ground and power planes
2018-08-28 21:14:49 +00:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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(xy 133.223 44.847689) (xy 133.114577 44.685423) (xy 132.639909 44.36826) (xy 132.221333 44.285) (xy 131.938667 44.285)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 131.520091 44.36826) (xy 131.045423 44.685423) (xy 130.895365 44.91) (xy 129.927987 44.91) (xy 129.888739 44.851261)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
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make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
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add ground and power planes
2018-08-28 21:14:49 +00:00
(xy 124.808739 52.471261) (xy 124.527727 52.283495) (xy 124.19625 52.21756) (xy 123.75875 52.21756) (xy 123.427273 52.283495)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
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(xy 104.291182 75.3) (xy 103.988818 75.3) (xy 103.541073 75.389062) (xy 103.033327 75.728327) (xy 102.87 75.972763)
(xy 102.706673 75.728327) (xy 102.198927 75.389062) (xy 101.751182 75.3) (xy 101.448818 75.3) (xy 101.001073 75.389062)
(xy 100.695 75.593573) (xy 100.695 73.631427) (xy 101.001073 73.835938) (xy 101.448818 73.925) (xy 101.751182 73.925)
(xy 102.198927 73.835938) (xy 102.706673 73.496673) (xy 102.87 73.252237) (xy 103.033327 73.496673) (xy 103.541073 73.835938)
(xy 103.988818 73.925) (xy 104.291182 73.925) (xy 104.738927 73.835938) (xy 105.246673 73.496673) (xy 105.444904 73.2)
(xy 119.554227 73.2) (xy 119.634 73.215868) (xy 119.713773 73.2) (xy 119.713774 73.2) (xy 119.950046 73.153003)
(xy 120.217977 72.973977) (xy 120.263168 72.906344) (xy 121.522513 71.647) (xy 121.617874 71.647) (xy 121.99828 71.489431)
(xy 122.289431 71.19828) (xy 122.447 70.817874) (xy 122.447 70.406126) (xy 122.338379 70.143892) (xy 123.1675 70.973013)
(xy 123.167501 78.685722) (xy 123.1675 78.685727) (xy 123.167501 82.907002) (xy 122.952727 82.763495) (xy 122.62125 82.69756)
(xy 122.18375 82.69756) (xy 121.852273 82.763495) (xy 121.571261 82.951261) (xy 121.383495 83.232273) (xy 121.31756 83.56375)
(xy 121.31756 84.07625) (xy 121.383495 84.407727) (xy 121.571261 84.688739) (xy 121.852273 84.876505) (xy 122.18375 84.94244)
(xy 122.62125 84.94244) (xy 122.952727 84.876505) (xy 123.19 84.717964) (xy 123.427273 84.876505) (xy 123.75875 84.94244)
(xy 124.19625 84.94244) (xy 124.527727 84.876505) (xy 124.808739 84.688739) (xy 124.847987 84.63) (xy 130.895365 84.63)
(xy 131.045423 84.854577) (xy 131.397758 85.09) (xy 131.045423 85.325423) (xy 130.895365 85.55) (xy 129.927987 85.55)
(xy 129.888739 85.491261) (xy 129.607727 85.303495) (xy 129.27625 85.23756) (xy 128.83875 85.23756) (xy 128.507273 85.303495)
(xy 128.344969 85.411943) (xy 128.279698 85.346673) (xy 128.046309 85.25) (xy 127.76825 85.25) (xy 127.6095 85.40875)
(xy 127.6095 86.233) (xy 127.6295 86.233) (xy 127.6295 86.487) (xy 127.6095 86.487) (xy 127.6095 87.31125)
(xy 127.76825 87.47) (xy 128.046309 87.47) (xy 128.279698 87.373327) (xy 128.344969 87.308057) (xy 128.507273 87.416505)
(xy 128.83875 87.48244) (xy 129.27625 87.48244) (xy 129.607727 87.416505) (xy 129.888739 87.228739) (xy 129.927987 87.17)
(xy 130.895365 87.17) (xy 131.045423 87.394577) (xy 131.397758 87.63) (xy 131.045423 87.865423) (xy 130.895365 88.09)
(xy 124.847987 88.09) (xy 124.808739 88.031261) (xy 124.7875 88.01707) (xy 124.7875 87.481269) (xy 124.803367 87.401499)
(xy 124.7875 87.32173) (xy 124.7875 87.321726) (xy 124.740503 87.085454) (xy 124.561477 86.817523) (xy 124.493847 86.772334)
(xy 124.367263 86.64575) (xy 126.41 86.64575) (xy 126.41 86.96131) (xy 126.506673 87.194699) (xy 126.685302 87.373327)
(xy 126.918691 87.47) (xy 127.19675 87.47) (xy 127.3555 87.31125) (xy 127.3555 86.487) (xy 126.56875 86.487)
(xy 126.41 86.64575) (xy 124.367263 86.64575) (xy 123.565168 85.843656) (xy 123.519977 85.776023) (xy 123.494037 85.75869)
(xy 126.41 85.75869) (xy 126.41 86.07425) (xy 126.56875 86.233) (xy 127.3555 86.233) (xy 127.3555 85.40875)
(xy 127.19675 85.25) (xy 126.918691 85.25) (xy 126.685302 85.346673) (xy 126.506673 85.525301) (xy 126.41 85.75869)
(xy 123.494037 85.75869) (xy 123.252046 85.596997) (xy 123.015774 85.55) (xy 123.015773 85.55) (xy 122.936 85.534132)
(xy 122.856227 85.55) (xy 120.223513 85.55) (xy 118.666 83.992488) (xy 118.666 81.933711) (xy 118.733431 81.86628)
add ground and power planes
2018-08-28 21:14:49 +00:00
(xy 118.891 81.485874) (xy 118.891 81.074126) (xy 118.733431 80.69372) (xy 118.44228 80.402569) (xy 118.061874 80.245)
(xy 117.650126 80.245) (xy 117.26972 80.402569) (xy 116.978569 80.69372) (xy 116.821 81.074126) (xy 116.821 81.485874)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 116.978569 81.86628) (xy 117.046001 81.933712) (xy 117.046 84.248227) (xy 117.030132 84.328) (xy 117.046 84.407773)
(xy 117.092997 84.644045) (xy 117.272023 84.911977) (xy 117.339656 84.957168) (xy 119.258834 86.876347) (xy 119.304023 86.943977)
(xy 119.571954 87.123003) (xy 119.808226 87.17) (xy 119.808227 87.17) (xy 119.888 87.185868) (xy 119.967773 87.17)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 122.600488 87.17) (xy 123.167501 87.737013) (xy 123.167501 87.987002) (xy 122.952727 87.843495) (xy 122.62125 87.77756)
(xy 122.18375 87.77756) (xy 121.852273 87.843495) (xy 121.571261 88.031261) (xy 121.383495 88.312273) (xy 121.31756 88.64375)
(xy 121.31756 89.15625) (xy 121.383495 89.487727) (xy 121.571261 89.768739) (xy 121.852273 89.956505) (xy 122.18375 90.02244)
(xy 122.62125 90.02244) (xy 122.952727 89.956505) (xy 123.19 89.797964) (xy 123.427273 89.956505) (xy 123.75875 90.02244)
(xy 124.19625 90.02244) (xy 124.527727 89.956505) (xy 124.808739 89.768739) (xy 124.847987 89.71) (xy 130.895365 89.71)
(xy 131.045423 89.934577) (xy 131.397758 90.17) (xy 131.045423 90.405423) (xy 130.895365 90.63) (xy 129.927987 90.63)
(xy 129.888739 90.571261) (xy 129.607727 90.383495) (xy 129.27625 90.31756) (xy 128.83875 90.31756) (xy 128.507273 90.383495)
(xy 128.344969 90.491943) (xy 128.279698 90.426673) (xy 128.046309 90.33) (xy 127.76825 90.33) (xy 127.6095 90.48875)
(xy 127.6095 91.313) (xy 127.6295 91.313) (xy 127.6295 91.567) (xy 127.6095 91.567) (xy 127.6095 92.39125)
(xy 127.76825 92.55) (xy 128.046309 92.55) (xy 128.279698 92.453327) (xy 128.344969 92.388057) (xy 128.507273 92.496505)
(xy 128.83875 92.56244) (xy 129.27625 92.56244) (xy 129.607727 92.496505) (xy 129.888739 92.308739) (xy 129.927987 92.25)
(xy 130.895365 92.25) (xy 131.045423 92.474577) (xy 131.397758 92.71) (xy 131.045423 92.945423) (xy 130.895365 93.17)
(xy 124.847987 93.17) (xy 124.808739 93.111261) (xy 124.527727 92.923495) (xy 124.19625 92.85756) (xy 123.75875 92.85756)
(xy 123.427273 92.923495) (xy 123.19 93.082036) (xy 122.952727 92.923495) (xy 122.62125 92.85756) (xy 122.18375 92.85756)
(xy 121.852273 92.923495) (xy 121.571261 93.111261) (xy 121.383495 93.392273) (xy 121.31756 93.72375) (xy 121.31756 94.23625)
(xy 121.383495 94.567727) (xy 121.571261 94.848739) (xy 121.852273 95.036505) (xy 122.18375 95.10244) (xy 122.62125 95.10244)
(xy 122.952727 95.036505) (xy 123.167501 94.892998) (xy 123.167501 95.142987) (xy 122.600488 95.71) (xy 121.491769 95.71)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 121.411999 95.694133) (xy 121.33223 95.71) (xy 121.332226 95.71) (xy 121.095954 95.756997) (xy 120.828023 95.936023)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 120.782834 96.003653) (xy 117.339656 99.446832) (xy 117.272023 99.492023) (xy 117.092997 99.759955) (xy 117.076054 99.845136)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 117.030132 100.076) (xy 117.046 100.155774) (xy 117.046001 101.715484) (xy 115.431486 103.33) (xy 111.839769 103.33)
(xy 111.759999 103.314133) (xy 111.68023 103.33) (xy 111.680226 103.33) (xy 111.443954 103.376997) (xy 111.176023 103.556023)
(xy 111.130834 103.623653) (xy 108.093488 106.661) (xy 107.998126 106.661) (xy 107.61772 106.818569) (xy 107.326569 107.10972)
(xy 107.169 107.490126) (xy 107.169 107.901874) (xy 107.326569 108.28228) (xy 107.61772 108.573431) (xy 107.998126 108.731)
(xy 108.409874 108.731) (xy 108.79028 108.573431) (xy 109.081431 108.28228) (xy 109.239 107.901874) (xy 109.239 107.806512)
(xy 112.095513 104.95) (xy 115.687225 104.95) (xy 115.766998 104.965868) (xy 115.846771 104.95) (xy 115.846772 104.95)
(xy 116.083044 104.903003) (xy 116.350975 104.723977) (xy 116.396166 104.656344) (xy 118.200561 102.85195) (xy 118.439977 102.691977)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 118.619003 102.424046) (xy 118.681868 102.108) (xy 118.666 102.028226) (xy 118.666 100.411512) (xy 121.747513 97.33)
(xy 122.856227 97.33) (xy 122.936 97.345868) (xy 123.015773 97.33) (xy 123.015774 97.33) (xy 123.252046 97.283003)
(xy 123.519977 97.103977) (xy 123.565168 97.036344) (xy 123.795762 96.80575) (xy 126.41 96.80575) (xy 126.41 97.12131)
(xy 126.506673 97.354699) (xy 126.685302 97.533327) (xy 126.918691 97.63) (xy 127.19675 97.63) (xy 127.3555 97.47125)
(xy 127.3555 96.647) (xy 126.56875 96.647) (xy 126.41 96.80575) (xy 123.795762 96.80575) (xy 124.493847 96.107666)
(xy 124.561477 96.062477) (xy 124.657552 95.91869) (xy 126.41 95.91869) (xy 126.41 96.23425) (xy 126.56875 96.393)
(xy 127.3555 96.393) (xy 127.3555 95.56875) (xy 127.19675 95.41) (xy 126.918691 95.41) (xy 126.685302 95.506673)
(xy 126.506673 95.685301) (xy 126.41 95.91869) (xy 124.657552 95.91869) (xy 124.740503 95.794546) (xy 124.7875 95.558274)
(xy 124.7875 95.55827) (xy 124.803367 95.478501) (xy 124.7875 95.398731) (xy 124.7875 94.86293) (xy 124.808739 94.848739)
(xy 124.847987 94.79) (xy 130.895365 94.79) (xy 131.045423 95.014577) (xy 131.397758 95.25) (xy 131.045423 95.485423)
(xy 130.895365 95.71) (xy 129.927987 95.71) (xy 129.888739 95.651261) (xy 129.607727 95.463495) (xy 129.27625 95.39756)
(xy 128.83875 95.39756) (xy 128.507273 95.463495) (xy 128.344969 95.571943) (xy 128.279698 95.506673) (xy 128.046309 95.41)
(xy 127.76825 95.41) (xy 127.6095 95.56875) (xy 127.6095 96.393) (xy 127.6295 96.393) (xy 127.6295 96.647)
(xy 127.6095 96.647) (xy 127.6095 97.47125) (xy 127.76825 97.63) (xy 128.046309 97.63) (xy 128.279698 97.533327)
(xy 128.344969 97.468057) (xy 128.507273 97.576505) (xy 128.83875 97.64244) (xy 129.27625 97.64244) (xy 129.607727 97.576505)
(xy 129.888739 97.388739) (xy 129.927987 97.33) (xy 130.895365 97.33) (xy 131.045423 97.554577) (xy 131.397758 97.79)
(xy 131.045423 98.025423) (xy 130.895365 98.25) (xy 124.847987 98.25) (xy 124.808739 98.191261) (xy 124.527727 98.003495)
(xy 124.19625 97.93756) (xy 123.75875 97.93756) (xy 123.427273 98.003495) (xy 123.19 98.162036) (xy 122.952727 98.003495)
(xy 122.62125 97.93756) (xy 122.18375 97.93756) (xy 121.852273 98.003495) (xy 121.571261 98.191261) (xy 121.383495 98.472273)
(xy 121.31756 98.80375) (xy 121.31756 99.31625) (xy 121.383495 99.647727) (xy 121.571261 99.928739) (xy 121.806241 100.085747)
(xy 115.005988 106.886) (xy 113.937711 106.886) (xy 113.87028 106.818569) (xy 113.489874 106.661) (xy 113.078126 106.661)
(xy 112.69772 106.818569) (xy 112.406569 107.10972) (xy 112.249 107.490126) (xy 112.249 107.901874) (xy 112.406569 108.28228)
(xy 112.69772 108.573431) (xy 113.078126 108.731) (xy 113.489874 108.731) (xy 113.87028 108.573431) (xy 113.937711 108.506)
(xy 115.261727 108.506) (xy 115.3415 108.521868) (xy 115.421273 108.506) (xy 115.421274 108.506) (xy 115.657546 108.459003)
(xy 115.925477 108.279977) (xy 115.970668 108.212344) (xy 124.000572 100.18244) (xy 124.19625 100.18244) (xy 124.527727 100.116505)
(xy 124.808739 99.928739) (xy 124.847987 99.87) (xy 130.895365 99.87) (xy 131.045423 100.094577) (xy 131.520091 100.41174)
(xy 131.938667 100.495) (xy 132.221333 100.495) (xy 132.639909 100.41174) (xy 133.114577 100.094577) (xy 133.223 99.932311)
(xy 133.223 109.617689) (xy 133.114577 109.455423) (xy 132.639909 109.13826) (xy 132.221333 109.055) (xy 131.938667 109.055)
(xy 131.520091 109.13826) (xy 131.045423 109.455423) (xy 130.895365 109.68) (xy 129.927987 109.68) (xy 129.888739 109.621261)
(xy 129.607727 109.433495) (xy 129.27625 109.36756) (xy 128.83875 109.36756) (xy 128.507273 109.433495) (xy 128.344969 109.541943)
(xy 128.279698 109.476673) (xy 128.046309 109.38) (xy 127.76825 109.38) (xy 127.6095 109.53875) (xy 127.6095 110.363)
(xy 127.6295 110.363) (xy 127.6295 110.617) (xy 127.6095 110.617) (xy 127.6095 111.44125) (xy 127.76825 111.6)
(xy 128.046309 111.6) (xy 128.279698 111.503327) (xy 128.344969 111.438057) (xy 128.507273 111.546505) (xy 128.83875 111.61244)
(xy 129.27625 111.61244) (xy 129.607727 111.546505) (xy 129.888739 111.358739) (xy 129.927987 111.3) (xy 130.895365 111.3)
(xy 131.045423 111.524577) (xy 131.397758 111.76) (xy 131.045423 111.995423) (xy 130.895365 112.22) (xy 124.847987 112.22)
(xy 124.808739 112.161261) (xy 124.7875 112.14707) (xy 124.7875 111.865274) (xy 124.803368 111.7855) (xy 124.740503 111.469453)
(xy 124.606665 111.269152) (xy 124.561477 111.201523) (xy 124.493847 111.156334) (xy 124.113263 110.77575) (xy 126.41 110.77575)
(xy 126.41 111.09131) (xy 126.506673 111.324699) (xy 126.685302 111.503327) (xy 126.918691 111.6) (xy 127.19675 111.6)
(xy 127.3555 111.44125) (xy 127.3555 110.617) (xy 126.56875 110.617) (xy 126.41 110.77575) (xy 124.113263 110.77575)
(xy 123.311168 109.973656) (xy 123.265977 109.906023) (xy 123.240037 109.88869) (xy 126.41 109.88869) (xy 126.41 110.20425)
(xy 126.56875 110.363) (xy 127.3555 110.363) (xy 127.3555 109.53875) (xy 127.19675 109.38) (xy 126.918691 109.38)
(xy 126.685302 109.476673) (xy 126.506673 109.655301) (xy 126.41 109.88869) (xy 123.240037 109.88869) (xy 122.998046 109.726997)
(xy 122.761774 109.68) (xy 122.761773 109.68) (xy 122.682 109.664132) (xy 122.602227 109.68) (xy 105.444904 109.68)
(xy 105.246673 109.383327) (xy 104.738927 109.044062) (xy 104.291182 108.955) (xy 103.988818 108.955) (xy 103.541073 109.044062)
(xy 103.033327 109.383327) (xy 102.87 109.627763) (xy 102.706673 109.383327) (xy 102.198927 109.044062) (xy 101.751182 108.955)
(xy 101.448818 108.955) (xy 101.001073 109.044062) (xy 100.695 109.248573) (xy 100.695 107.286427) (xy 101.001073 107.490938)
(xy 101.448818 107.58) (xy 101.751182 107.58) (xy 102.198927 107.490938) (xy 102.706673 107.151673) (xy 102.87 106.907237)
(xy 103.033327 107.151673) (xy 103.541073 107.490938) (xy 103.988818 107.58) (xy 104.291182 107.58) (xy 104.738927 107.490938)
(xy 105.246673 107.151673) (xy 105.585938 106.643927) (xy 105.705072 106.045) (xy 105.585938 105.446073) (xy 105.246673 104.938327)
(xy 104.738927 104.599062) (xy 104.291182 104.51) (xy 103.988818 104.51) (xy 103.541073 104.599062) (xy 103.033327 104.938327)
(xy 102.87 105.182763) (xy 102.706673 104.938327) (xy 102.198927 104.599062) (xy 101.751182 104.51) (xy 101.448818 104.51)
(xy 101.001073 104.599062) (xy 100.695 104.803573) (xy 100.695 102.841427) (xy 101.001073 103.045938) (xy 101.448818 103.135)
(xy 101.751182 103.135) (xy 102.198927 103.045938) (xy 102.706673 102.706673) (xy 102.87 102.462237) (xy 103.033327 102.706673)
(xy 103.541073 103.045938) (xy 103.988818 103.135) (xy 104.291182 103.135) (xy 104.738927 103.045938) (xy 105.246673 102.706673)
(xy 105.585938 102.198927) (xy 105.705072 101.6) (xy 105.585938 101.001073) (xy 105.246673 100.493327) (xy 104.738927 100.154062)
(xy 104.291182 100.065) (xy 103.988818 100.065) (xy 103.541073 100.154062) (xy 103.033327 100.493327) (xy 102.87 100.737763)
(xy 102.706673 100.493327) (xy 102.198927 100.154062) (xy 101.751182 100.065) (xy 101.448818 100.065) (xy 101.001073 100.154062)
(xy 100.695 100.358573) (xy 100.695 98.396427) (xy 101.001073 98.600938) (xy 101.448818 98.69) (xy 101.751182 98.69)
(xy 102.198927 98.600938) (xy 102.706673 98.261673) (xy 102.87 98.017237) (xy 103.033327 98.261673) (xy 103.541073 98.600938)
(xy 103.988818 98.69) (xy 104.291182 98.69) (xy 104.738927 98.600938) (xy 105.246673 98.261673) (xy 105.585938 97.753927)
(xy 105.705072 97.155) (xy 105.585938 96.556073) (xy 105.246673 96.048327) (xy 104.738927 95.709062) (xy 104.291182 95.62)
(xy 103.988818 95.62) (xy 103.541073 95.709062) (xy 103.033327 96.048327) (xy 102.87 96.292763) (xy 102.706673 96.048327)
(xy 102.198927 95.709062) (xy 101.751182 95.62) (xy 101.448818 95.62) (xy 101.001073 95.709062) (xy 100.557129 96.005696)
(xy 100.417809 95.797191) (xy 100.207765 95.656843) (xy 99.96 95.60756) (xy 99.661224 95.60756) (xy 99.06 95.487969)
(xy 98.458775 95.60756) (xy 98.16 95.60756) (xy 97.912235 95.656843) (xy 97.702191 95.797191) (xy 97.561843 96.007235)
(xy 97.51256 96.255) (xy 97.51256 96.553776) (xy 97.425 96.99397) (xy 97.425 98.14397) (xy 97.425001 101.438965)
(xy 97.425 101.43897) (xy 97.425001 105.883965) (xy 97.425 105.88397) (xy 97.425001 110.328965) (xy 97.425 110.32897)
(xy 97.425 111.47897) (xy 97.425001 114.773965) (xy 97.425 114.77397) (xy 97.425001 119.541031) (xy 97.51256 119.98122)
(xy 97.51256 120.28) (xy 97.561843 120.527765) (xy 97.702191 120.737809) (xy 97.912235 120.878157) (xy 98.16 120.92744)
(xy 98.458776 120.92744) (xy 99.06 121.047031) (xy 99.661225 120.92744) (xy 99.96 120.92744) (xy 100.207765 120.878157)
(xy 100.417809 120.737809) (xy 100.557129 120.529304) (xy 101.001073 120.825938) (xy 101.448818 120.915) (xy 101.751182 120.915)
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(xy 85.21744 103.323873) (xy 85.21744 102.12) (xy 85.168157 101.872235) (xy 85.027809 101.662191) (xy 84.817765 101.521843)
add ground and power planes
2018-08-28 21:14:49 +00:00
(xy 84.57 101.47256) (xy 83.07 101.47256) (xy 82.822235 101.521843) (xy 82.612191 101.662191) (xy 82.471843 101.872235)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 82.42256 102.12) (xy 79.673755 102.12) (xy 79.705 102.044569) (xy 79.705 101.155431) (xy 79.364741 100.333974)
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(xy 82.848483 74.451912) (xy 83.640395 73.66) (xy 83.999605 73.66) (xy 84.791517 74.451912) (xy 85.03246 74.383923)
(xy 85.217201 73.864829) (xy 85.18923 73.314552) (xy 85.03246 72.936077) (xy 84.791517 72.868088) (xy 83.999605 73.66)
(xy 83.640395 73.66) (xy 82.848483 72.868088) (xy 82.60754 72.936077) (xy 82.422799 73.455171) (xy 71.247 73.455171)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 71.247 66.865431) (xy 75.235 66.865431) (xy 75.235 67.754569) (xy 75.575259 68.576026) (xy 76.203974 69.204741)
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(xy 83.014844 69.966469) (xy 82.645853 70.33546) (xy 82.435 70.844506) (xy 82.435 71.395494) (xy 82.645853 71.90454)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 83.03546 72.294147) (xy 83.25093 72.383397) (xy 83.096077 72.44754) (xy 83.028088 72.688483) (xy 83.82 73.480395)
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(xy 85.568088 71.418483) (xy 86.36 72.210395) (xy 87.151912 71.418483) (xy 87.083923 71.17754) (xy 86.917342 71.118255)
add ground and power planes
2018-08-28 21:14:49 +00:00
(xy 87.14454 71.024147) (xy 87.534147 70.63454) (xy 87.745 70.125494) (xy 87.745 69.574506) (xy 87.534147 69.06546)
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changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 85.21744 67.83) (xy 85.168157 67.582235) (xy 85.027809 67.372191) (xy 84.817765 67.231843) (xy 84.57 67.18256)
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)
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(filled_polygon
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add ground and power planes
2018-08-28 21:14:49 +00:00
)
)
)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(zone (net 2) (net_name GND) (layer B.Cu) (tstamp 5B985751) (hatch edge 0.508)
add ground and power planes
2018-08-28 21:14:49 +00:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 228.6 40.64) (xy 228.6 116.84) (xy 210.82 116.84) (xy 195.58 132.08) (xy 138.43 132.08)
(xy 138.43 40.64)
add ground and power planes
2018-08-28 21:14:49 +00:00
)
)
(filled_polygon
(pts
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
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(xy 221.115 66.61505) (xy 221.115 67.36495) (xy 221.284741 67.774741) (xy 220.87495 67.605) (xy 220.12505 67.605)
(xy 219.432233 67.891974) (xy 218.901974 68.422233) (xy 218.615 69.11505) (xy 218.615 69.86495) (xy 218.901974 70.557767)
(xy 219.432233 71.088026) (xy 220.12505 71.375) (xy 220.87495 71.375) (xy 221.284741 71.205259) (xy 221.115 71.61505)
(xy 221.115 72.36495) (xy 221.284741 72.774741) (xy 220.87495 72.605) (xy 220.12505 72.605) (xy 219.432233 72.891974)
(xy 218.901974 73.422233) (xy 218.615 74.11505) (xy 218.615 74.86495) (xy 218.901974 75.557767) (xy 219.432233 76.088026)
(xy 220.12505 76.375) (xy 220.87495 76.375) (xy 221.284741 76.205259) (xy 221.115 76.61505) (xy 221.115 77.36495)
(xy 221.284741 77.774741) (xy 220.87495 77.605) (xy 220.12505 77.605) (xy 219.432233 77.891974) (xy 218.901974 78.422233)
(xy 218.615 79.11505) (xy 218.615 79.86495) (xy 218.901974 80.557767) (xy 219.432233 81.088026) (xy 220.12505 81.375)
(xy 220.87495 81.375) (xy 221.284741 81.205259) (xy 221.115 81.61505) (xy 221.115 82.36495) (xy 221.284741 82.774741)
(xy 220.87495 82.605) (xy 220.12505 82.605) (xy 219.432233 82.891974) (xy 218.901974 83.422233) (xy 218.615 84.11505)
(xy 218.615 84.86495) (xy 218.901974 85.557767) (xy 219.432233 86.088026) (xy 220.12505 86.375) (xy 220.87495 86.375)
(xy 221.284741 86.205259) (xy 221.115 86.61505) (xy 221.115 87.36495) (xy 221.284741 87.774741) (xy 220.87495 87.605)
(xy 220.12505 87.605) (xy 219.432233 87.891974) (xy 218.901974 88.422233) (xy 218.615 89.11505) (xy 218.615 89.86495)
(xy 218.901974 90.557767) (xy 219.432233 91.088026) (xy 220.12505 91.375) (xy 220.87495 91.375) (xy 221.284741 91.205259)
(xy 221.115 91.61505) (xy 221.115 92.36495) (xy 221.284741 92.774741) (xy 220.87495 92.605) (xy 220.12505 92.605)
(xy 219.432233 92.891974) (xy 218.901974 93.422233) (xy 218.615 94.11505) (xy 218.615 94.86495) (xy 218.901974 95.557767)
(xy 219.432233 96.088026) (xy 220.12505 96.375) (xy 220.87495 96.375) (xy 221.284741 96.205259) (xy 221.115 96.61505)
(xy 221.115 97.36495) (xy 221.284741 97.774741) (xy 220.87495 97.605) (xy 220.12505 97.605) (xy 219.432233 97.891974)
(xy 218.901974 98.422233) (xy 218.615 99.11505) (xy 218.615 99.86495) (xy 218.901974 100.557767) (xy 219.432233 101.088026)
(xy 220.12505 101.375) (xy 220.87495 101.375) (xy 221.284741 101.205259) (xy 221.115 101.61505) (xy 221.115 102.36495)
(xy 221.284741 102.774741) (xy 220.87495 102.605) (xy 220.12505 102.605) (xy 219.432233 102.891974) (xy 218.901974 103.422233)
(xy 218.615 104.11505) (xy 218.615 104.86495) (xy 218.901974 105.557767) (xy 219.432233 106.088026) (xy 220.12505 106.375)
(xy 220.87495 106.375) (xy 221.284741 106.205259) (xy 221.115 106.61505) (xy 221.115 107.36495) (xy 221.284741 107.774741)
(xy 220.87495 107.605) (xy 220.12505 107.605) (xy 219.432233 107.891974) (xy 218.901974 108.422233) (xy 218.615 109.11505)
(xy 218.615 109.86495) (xy 218.901974 110.557767) (xy 219.432233 111.088026) (xy 220.12505 111.375) (xy 220.87495 111.375)
(xy 221.284741 111.205259) (xy 221.115 111.61505) (xy 221.115 112.36495) (xy 221.284741 112.774741) (xy 220.87495 112.605)
(xy 220.12505 112.605) (xy 219.432233 112.891974) (xy 218.901974 113.422233) (xy 218.615 114.11505) (xy 218.615 114.86495)
(xy 218.901974 115.557767) (xy 219.432233 116.088026) (xy 220.12505 116.375) (xy 220.87495 116.375) (xy 221.284741 116.205259)
(xy 221.115 116.61505) (xy 221.115 116.713) (xy 210.82 116.713) (xy 210.771399 116.722667) (xy 210.730197 116.750197)
(xy 195.527394 131.953) (xy 138.557 131.953) (xy 138.557 129.604523) (xy 138.652235 129.668157) (xy 138.9 129.71744)
(xy 140.5 129.71744) (xy 140.747765 129.668157) (xy 140.957809 129.527809) (xy 141.098157 129.317765) (xy 141.14744 129.07)
(xy 141.14744 127.47) (xy 141.137495 127.42) (xy 153.44256 127.42) (xy 153.44256 129.12) (xy 153.491843 129.367765)
(xy 153.632191 129.577809) (xy 153.842235 129.718157) (xy 154.09 129.76744) (xy 155.79 129.76744) (xy 156.037765 129.718157)
(xy 156.247809 129.577809) (xy 156.388157 129.367765) (xy 156.43744 129.12) (xy 156.43744 127.42) (xy 156.388157 127.172235)
(xy 156.247809 126.962191) (xy 156.037765 126.821843) (xy 155.79 126.77256) (xy 154.09 126.77256) (xy 153.842235 126.821843)
(xy 153.632191 126.962191) (xy 153.491843 127.172235) (xy 153.44256 127.42) (xy 141.137495 127.42) (xy 141.098157 127.222235)
(xy 140.957809 127.012191) (xy 140.747765 126.871843) (xy 140.613894 126.845215) (xy 140.734577 126.764577) (xy 141.05174 126.289909)
(xy 141.163113 125.73) (xy 141.05174 125.170091) (xy 140.734577 124.695423) (xy 140.382242 124.46) (xy 140.734577 124.224577)
(xy 141.05174 123.749909) (xy 141.163113 123.19) (xy 141.05174 122.630091) (xy 140.857908 122.34) (xy 153.44256 122.34)
(xy 153.44256 124.04) (xy 153.491843 124.287765) (xy 153.632191 124.497809) (xy 153.842235 124.638157) (xy 154.09 124.68744)
(xy 155.79 124.68744) (xy 156.037765 124.638157) (xy 156.247809 124.497809) (xy 156.388157 124.287765) (xy 156.43744 124.04)
(xy 156.43744 122.34) (xy 156.388157 122.092235) (xy 156.247809 121.882191) (xy 156.037765 121.741843) (xy 155.79 121.69256)
(xy 154.09 121.69256) (xy 153.842235 121.741843) (xy 153.632191 121.882191) (xy 153.491843 122.092235) (xy 153.44256 122.34)
(xy 140.857908 122.34) (xy 140.734577 122.155423) (xy 140.382242 121.92) (xy 140.734577 121.684577) (xy 141.05174 121.209909)
(xy 141.163113 120.65) (xy 141.05174 120.090091) (xy 140.734577 119.615423) (xy 140.382242 119.38) (xy 140.734577 119.144577)
(xy 141.05174 118.669909) (xy 141.163113 118.11) (xy 141.05174 117.550091) (xy 140.857908 117.26) (xy 153.44256 117.26)
(xy 153.44256 118.96) (xy 153.491843 119.207765) (xy 153.632191 119.417809) (xy 153.842235 119.558157) (xy 154.09 119.60744)
(xy 155.79 119.60744) (xy 156.037765 119.558157) (xy 156.247809 119.417809) (xy 156.388157 119.207765) (xy 156.43744 118.96)
(xy 156.43744 117.26) (xy 156.388157 117.012235) (xy 156.247809 116.802191) (xy 156.037765 116.661843) (xy 155.79 116.61256)
(xy 154.09 116.61256) (xy 153.842235 116.661843) (xy 153.632191 116.802191) (xy 153.491843 117.012235) (xy 153.44256 117.26)
(xy 140.857908 117.26) (xy 140.734577 117.075423) (xy 140.382242 116.84) (xy 140.734577 116.604577) (xy 141.05174 116.129909)
(xy 141.163113 115.57) (xy 141.05174 115.010091) (xy 140.734577 114.535423) (xy 140.382242 114.3) (xy 140.734577 114.064577)
(xy 141.05174 113.589909) (xy 141.163113 113.03) (xy 141.05174 112.470091) (xy 140.857908 112.18) (xy 153.44256 112.18)
(xy 153.44256 113.88) (xy 153.491843 114.127765) (xy 153.632191 114.337809) (xy 153.842235 114.478157) (xy 154.09 114.52744)
(xy 155.79 114.52744) (xy 156.037765 114.478157) (xy 156.247809 114.337809) (xy 156.388157 114.127765) (xy 156.43744 113.88)
(xy 156.43744 112.18) (xy 156.388157 111.932235) (xy 156.247809 111.722191) (xy 156.037765 111.581843) (xy 155.79 111.53256)
(xy 154.09 111.53256) (xy 153.842235 111.581843) (xy 153.632191 111.722191) (xy 153.491843 111.932235) (xy 153.44256 112.18)
(xy 140.857908 112.18) (xy 140.734577 111.995423) (xy 140.382242 111.76) (xy 140.734577 111.524577) (xy 141.05174 111.049909)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 141.077754 110.919126) (xy 173.59 110.919126) (xy 173.59 111.330874) (xy 173.747569 111.71128) (xy 173.815 111.778711)
(xy 173.815001 116.186288) (xy 173.747569 116.25372) (xy 173.59 116.634126) (xy 173.59 117.045874) (xy 173.747569 117.42628)
(xy 174.03872 117.717431) (xy 174.419126 117.875) (xy 174.830874 117.875) (xy 175.21128 117.717431) (xy 175.502431 117.42628)
(xy 175.66 117.045874) (xy 175.66 116.634126) (xy 175.639402 116.584398) (xy 175.689126 116.604994) (xy 176.100874 116.604994)
(xy 176.48128 116.447425) (xy 176.772431 116.156274) (xy 176.93 115.775868) (xy 176.93 115.36412) (xy 176.883414 115.251651)
(xy 176.995881 115.298236) (xy 177.407629 115.298236) (xy 177.788035 115.140667) (xy 178.079186 114.849516) (xy 178.236755 114.46911)
(xy 178.236755 114.057362) (xy 178.079186 113.676956) (xy 177.975 113.57277) (xy 177.975 111.778711) (xy 178.042431 111.71128)
(xy 178.2 111.330874) (xy 178.2 110.919126) (xy 178.042431 110.53872) (xy 177.75128 110.247569) (xy 177.370874 110.09)
(xy 176.959126 110.09) (xy 176.57872 110.247569) (xy 176.53 110.296289) (xy 176.48128 110.247569) (xy 176.100874 110.09)
(xy 175.689126 110.09) (xy 175.30872 110.247569) (xy 175.26 110.296289) (xy 175.21128 110.247569) (xy 174.830874 110.09)
(xy 174.419126 110.09) (xy 174.03872 110.247569) (xy 173.747569 110.53872) (xy 173.59 110.919126) (xy 141.077754 110.919126)
(xy 141.163113 110.49) (xy 141.05174 109.930091) (xy 140.734577 109.455423) (xy 140.259909 109.13826) (xy 139.841333 109.055)
(xy 139.558667 109.055) (xy 139.140091 109.13826) (xy 138.665423 109.455423) (xy 138.557 109.617689) (xy 138.557 100.394523)
(xy 138.652235 100.458157) (xy 138.9 100.50744) (xy 140.5 100.50744) (xy 140.747765 100.458157) (xy 140.957809 100.317809)
(xy 141.098157 100.107765) (xy 141.14744 99.86) (xy 141.14744 98.26) (xy 141.137495 98.21) (xy 153.44256 98.21)
(xy 153.44256 99.91) (xy 153.491843 100.157765) (xy 153.632191 100.367809) (xy 153.842235 100.508157) (xy 154.09 100.55744)
(xy 155.79 100.55744) (xy 156.037765 100.508157) (xy 156.247809 100.367809) (xy 156.388157 100.157765) (xy 156.43744 99.91)
(xy 156.43744 98.21) (xy 156.388157 97.962235) (xy 156.247809 97.752191) (xy 156.037765 97.611843) (xy 155.79 97.56256)
(xy 154.09 97.56256) (xy 153.842235 97.611843) (xy 153.632191 97.752191) (xy 153.491843 97.962235) (xy 153.44256 98.21)
(xy 141.137495 98.21) (xy 141.098157 98.012235) (xy 140.957809 97.802191) (xy 140.747765 97.661843) (xy 140.613894 97.635215)
(xy 140.734577 97.554577) (xy 141.05174 97.079909) (xy 141.163113 96.52) (xy 141.05174 95.960091) (xy 140.734577 95.485423)
(xy 140.382242 95.25) (xy 140.734577 95.014577) (xy 141.05174 94.539909) (xy 141.163113 93.98) (xy 141.05174 93.420091)
(xy 140.857908 93.13) (xy 153.44256 93.13) (xy 153.44256 94.83) (xy 153.491843 95.077765) (xy 153.632191 95.287809)
(xy 153.842235 95.428157) (xy 154.09 95.47744) (xy 155.79 95.47744) (xy 156.037765 95.428157) (xy 156.247809 95.287809)
(xy 156.388157 95.077765) (xy 156.43744 94.83) (xy 156.43744 93.13) (xy 156.388157 92.882235) (xy 156.247809 92.672191)
(xy 156.037765 92.531843) (xy 155.79 92.48256) (xy 154.09 92.48256) (xy 153.842235 92.531843) (xy 153.632191 92.672191)
(xy 153.491843 92.882235) (xy 153.44256 93.13) (xy 140.857908 93.13) (xy 140.734577 92.945423) (xy 140.382242 92.71)
(xy 140.734577 92.474577) (xy 141.05174 91.999909) (xy 141.163113 91.44) (xy 141.05174 90.880091) (xy 140.734577 90.405423)
(xy 140.382242 90.17) (xy 140.734577 89.934577) (xy 141.05174 89.459909) (xy 141.163113 88.9) (xy 141.05174 88.340091)
(xy 140.857908 88.05) (xy 153.44256 88.05) (xy 153.44256 89.75) (xy 153.491843 89.997765) (xy 153.632191 90.207809)
(xy 153.842235 90.348157) (xy 154.09 90.39744) (xy 155.79 90.39744) (xy 156.037765 90.348157) (xy 156.247809 90.207809)
(xy 156.388157 89.997765) (xy 156.43744 89.75) (xy 156.43744 88.05) (xy 156.388157 87.802235) (xy 156.247809 87.592191)
(xy 156.037765 87.451843) (xy 155.79 87.40256) (xy 154.09 87.40256) (xy 153.842235 87.451843) (xy 153.632191 87.592191)
(xy 153.491843 87.802235) (xy 153.44256 88.05) (xy 140.857908 88.05) (xy 140.734577 87.865423) (xy 140.382242 87.63)
(xy 140.734577 87.394577) (xy 141.05174 86.919909) (xy 141.163113 86.36) (xy 141.05174 85.800091) (xy 140.734577 85.325423)
(xy 140.382242 85.09) (xy 140.734577 84.854577) (xy 141.05174 84.379909) (xy 141.163113 83.82) (xy 141.05174 83.260091)
(xy 140.857908 82.97) (xy 153.44256 82.97) (xy 153.44256 84.67) (xy 153.491843 84.917765) (xy 153.632191 85.127809)
(xy 153.842235 85.268157) (xy 154.09 85.31744) (xy 155.79 85.31744) (xy 156.037765 85.268157) (xy 156.247809 85.127809)
(xy 156.388157 84.917765) (xy 156.43744 84.67) (xy 156.43744 82.97) (xy 156.388157 82.722235) (xy 156.247809 82.512191)
(xy 156.037765 82.371843) (xy 155.79 82.32256) (xy 154.09 82.32256) (xy 153.842235 82.371843) (xy 153.632191 82.512191)
(xy 153.491843 82.722235) (xy 153.44256 82.97) (xy 140.857908 82.97) (xy 140.734577 82.785423) (xy 140.382242 82.55)
(xy 140.734577 82.314577) (xy 141.05174 81.839909) (xy 141.163113 81.28) (xy 141.05174 80.720091) (xy 140.734577 80.245423)
(xy 140.259909 79.92826) (xy 139.841333 79.845) (xy 139.558667 79.845) (xy 139.140091 79.92826) (xy 138.665423 80.245423)
(xy 138.557 80.407689) (xy 138.557 77.89) (xy 166.14256 77.89) (xy 166.14256 79.59) (xy 166.191843 79.837765)
(xy 166.332191 80.047809) (xy 166.542235 80.188157) (xy 166.79 80.23744) (xy 168.49 80.23744) (xy 168.737765 80.188157)
(xy 168.91 80.073072) (xy 169.082235 80.188157) (xy 169.33 80.23744) (xy 171.03 80.23744) (xy 171.277765 80.188157)
(xy 171.45 80.073072) (xy 171.622235 80.188157) (xy 171.87 80.23744) (xy 173.57 80.23744) (xy 173.817765 80.188157)
(xy 173.99 80.073072) (xy 174.162235 80.188157) (xy 174.41 80.23744) (xy 176.11 80.23744) (xy 176.357765 80.188157)
(xy 176.567809 80.047809) (xy 176.708157 79.837765) (xy 176.75744 79.59) (xy 176.75744 77.89) (xy 176.708157 77.642235)
(xy 176.567809 77.432191) (xy 176.357765 77.291843) (xy 176.11 77.24256) (xy 174.41 77.24256) (xy 174.162235 77.291843)
(xy 173.99 77.406928) (xy 173.817765 77.291843) (xy 173.57 77.24256) (xy 171.87 77.24256) (xy 171.622235 77.291843)
(xy 171.45 77.406928) (xy 171.277765 77.291843) (xy 171.03 77.24256) (xy 169.33 77.24256) (xy 169.082235 77.291843)
(xy 168.91 77.406928) (xy 168.737765 77.291843) (xy 168.49 77.24256) (xy 166.79 77.24256) (xy 166.542235 77.291843)
(xy 166.332191 77.432191) (xy 166.191843 77.642235) (xy 166.14256 77.89) (xy 138.557 77.89) (xy 138.557 64.834523)
(xy 138.652235 64.898157) (xy 138.9 64.94744) (xy 140.5 64.94744) (xy 140.747765 64.898157) (xy 140.957809 64.757809)
(xy 141.098157 64.547765) (xy 141.14744 64.3) (xy 141.14744 62.7) (xy 141.137495 62.65) (xy 153.44256 62.65)
(xy 153.44256 64.35) (xy 153.491843 64.597765) (xy 153.632191 64.807809) (xy 153.842235 64.948157) (xy 154.09 64.99744)
(xy 155.79 64.99744) (xy 156.037765 64.948157) (xy 156.247809 64.807809) (xy 156.388157 64.597765) (xy 156.43744 64.35)
(xy 156.43744 64.31) (xy 182.544488 64.31) (xy 182.631018 64.396531) (xy 182.48 64.761122) (xy 182.48 65.17287)
(xy 182.637569 65.553276) (xy 182.92872 65.844427) (xy 183.309126 66.001996) (xy 183.720874 66.001996) (xy 184.10128 65.844427)
(xy 184.392431 65.553276) (xy 184.55 65.17287) (xy 184.55 64.761122) (xy 184.392431 64.380716) (xy 184.325 64.313285)
(xy 184.325 64.214774) (xy 184.340868 64.135) (xy 184.278003 63.818953) (xy 184.144165 63.618652) (xy 184.098977 63.551023)
(xy 184.031347 63.505834) (xy 183.509168 62.983655) (xy 183.463977 62.916023) (xy 183.196046 62.736997) (xy 182.959774 62.69)
(xy 182.959773 62.69) (xy 182.88 62.674132) (xy 182.800227 62.69) (xy 156.43744 62.69) (xy 156.43744 62.65)
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 156.388157 62.402235) (xy 156.247809 62.192191) (xy 156.037765 62.051843) (xy 155.79 62.00256) (xy 154.09 62.00256)
(xy 153.842235 62.051843) (xy 153.632191 62.192191) (xy 153.491843 62.402235) (xy 153.44256 62.65) (xy 141.137495 62.65)
(xy 141.098157 62.452235) (xy 140.957809 62.242191) (xy 140.747765 62.101843) (xy 140.613894 62.075215) (xy 140.734577 61.994577)
(xy 141.05174 61.519909) (xy 141.163113 60.96) (xy 141.05174 60.400091) (xy 140.734577 59.925423) (xy 140.382242 59.69)
(xy 140.734577 59.454577) (xy 141.05174 58.979909) (xy 141.163113 58.42) (xy 141.05174 57.860091) (xy 140.857908 57.57)
(xy 153.44256 57.57) (xy 153.44256 59.27) (xy 153.491843 59.517765) (xy 153.632191 59.727809) (xy 153.842235 59.868157)
(xy 154.09 59.91744) (xy 155.79 59.91744) (xy 156.037765 59.868157) (xy 156.247809 59.727809) (xy 156.388157 59.517765)
(xy 156.43744 59.27) (xy 156.43744 57.57) (xy 156.388157 57.322235) (xy 156.247809 57.112191) (xy 156.037765 56.971843)
(xy 155.79 56.92256) (xy 154.09 56.92256) (xy 153.842235 56.971843) (xy 153.632191 57.112191) (xy 153.491843 57.322235)
(xy 153.44256 57.57) (xy 140.857908 57.57) (xy 140.734577 57.385423) (xy 140.382242 57.15) (xy 140.734577 56.914577)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 141.05174 56.439909) (xy 141.163113 55.88) (xy 141.122163 55.674126) (xy 178.67 55.674126) (xy 178.67 56.085874)
(xy 178.827569 56.46628) (xy 178.895 56.533711) (xy 178.895001 59.671288) (xy 178.827569 59.73872) (xy 178.67 60.119126)
(xy 178.67 60.530874) (xy 178.827569 60.91128) (xy 179.11872 61.202431) (xy 179.499126 61.36) (xy 179.910874 61.36)
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add ground and power planes
2018-08-28 21:14:49 +00:00
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make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
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add ground and power planes
2018-08-28 21:14:49 +00:00
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increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
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add ground and power planes
2018-08-28 21:14:49 +00:00
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increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
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2018-09-11 21:24:05 +00:00
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changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
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(xy 141.098157 64.547765) (xy 141.145451 64.31) (xy 153.44256 64.31) (xy 153.44256 64.35) (xy 153.491843 64.597765)
(xy 153.632191 64.807809) (xy 153.842235 64.948157) (xy 154.09 64.99744) (xy 155.79 64.99744) (xy 156.037765 64.948157)
(xy 156.247809 64.807809) (xy 156.388157 64.597765) (xy 156.43744 64.35) (xy 156.43744 62.65) (xy 156.388157 62.402235)
(xy 156.247809 62.192191) (xy 156.037765 62.051843) (xy 155.79 62.00256) (xy 154.09 62.00256) (xy 153.842235 62.051843)
(xy 153.632191 62.192191) (xy 153.491843 62.402235) (xy 153.44256 62.65) (xy 153.44256 62.69) (xy 141.145451 62.69)
(xy 141.098157 62.452235) (xy 140.957809 62.242191) (xy 140.747765 62.101843) (xy 140.613894 62.075215) (xy 140.734577 61.994577)
(xy 140.884635 61.77) (xy 141.513888 61.77) (xy 141.698584 62.046416) (xy 141.987706 62.239602) (xy 142.32875 62.30744)
(xy 142.81625 62.30744) (xy 143.157294 62.239602) (xy 143.446416 62.046416) (xy 143.51 61.951256) (xy 143.573584 62.046416)
(xy 143.862706 62.239602) (xy 144.20375 62.30744) (xy 144.69125 62.30744) (xy 145.032294 62.239602) (xy 145.321416 62.046416)
(xy 145.506112 61.77) (xy 147.414513 61.77) (xy 147.453761 61.828739) (xy 147.734773 62.016505) (xy 148.06625 62.08244)
(xy 148.50375 62.08244) (xy 148.835227 62.016505) (xy 149.0725 61.857964) (xy 149.309773 62.016505) (xy 149.64125 62.08244)
(xy 150.07875 62.08244) (xy 150.410227 62.016505) (xy 150.666903 61.845) (xy 151.831993 61.845) (xy 152.194126 61.995)
(xy 152.605874 61.995) (xy 152.98628 61.837431) (xy 153.277431 61.54628) (xy 153.435 61.165874) (xy 153.435 60.754126)
(xy 153.277431 60.37372) (xy 152.98628 60.082569) (xy 152.605874 59.925) (xy 152.194126 59.925) (xy 151.831993 60.075)
(xy 150.666903 60.075) (xy 150.410227 59.903495) (xy 150.07875 59.83756) (xy 149.64125 59.83756) (xy 149.309773 59.903495)
(xy 149.0725 60.062036) (xy 148.835227 59.903495) (xy 148.50375 59.83756) (xy 148.06625 59.83756) (xy 147.734773 59.903495)
(xy 147.453761 60.091261) (xy 147.414513 60.15) (xy 145.506112 60.15) (xy 145.321416 59.873584) (xy 145.032294 59.680398)
(xy 144.69125 59.61256) (xy 144.20375 59.61256) (xy 143.862706 59.680398) (xy 143.573584 59.873584) (xy 143.51 59.968744)
(xy 143.446416 59.873584) (xy 143.157294 59.680398) (xy 142.81625 59.61256) (xy 142.32875 59.61256) (xy 141.987706 59.680398)
(xy 141.698584 59.873584) (xy 141.513888 60.15) (xy 140.884635 60.15) (xy 140.734577 59.925423) (xy 140.382242 59.69)
(xy 140.734577 59.454577) (xy 140.884635 59.23) (xy 153.44256 59.23) (xy 153.44256 59.27) (xy 153.491843 59.517765)
(xy 153.632191 59.727809) (xy 153.842235 59.868157) (xy 154.09 59.91744) (xy 155.79 59.91744) (xy 156.037765 59.868157)
(xy 156.247809 59.727809) (xy 156.388157 59.517765) (xy 156.43744 59.27) (xy 156.43744 59.23) (xy 180.639488 59.23)
(xy 180.719884 59.310397) (xy 180.38872 59.447569) (xy 180.34 59.496289) (xy 180.29128 59.447569) (xy 179.910874 59.29)
(xy 179.499126 59.29) (xy 179.11872 59.447569) (xy 178.827569 59.73872) (xy 178.67 60.119126) (xy 178.67 60.530874)
(xy 178.827569 60.91128) (xy 178.895001 60.978712) (xy 178.895 65.484773) (xy 178.895001 65.484778) (xy 178.895 82.499487)
(xy 177.794168 81.398656) (xy 177.748977 81.331023) (xy 177.481046 81.151997) (xy 177.244774 81.105) (xy 177.244773 81.105)
(xy 177.165 81.089132) (xy 177.085227 81.105) (xy 176.230513 81.105) (xy 176.07 80.944488) (xy 176.07 80.23744)
(xy 176.11 80.23744) (xy 176.357765 80.188157) (xy 176.567809 80.047809) (xy 176.708157 79.837765) (xy 176.75744 79.59)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 176.75744 77.89) (xy 176.708157 77.642235) (xy 176.567809 77.432191) (xy 176.357765 77.291843) (xy 176.11 77.24256)
(xy 174.41 77.24256) (xy 174.162235 77.291843) (xy 173.99 77.406928) (xy 173.817765 77.291843) (xy 173.57 77.24256)
(xy 171.87 77.24256) (xy 171.622235 77.291843) (xy 171.45 77.406928) (xy 171.277765 77.291843) (xy 171.03 77.24256)
(xy 169.33 77.24256) (xy 169.082235 77.291843) (xy 168.91 77.406928) (xy 168.737765 77.291843) (xy 168.49 77.24256)
(xy 166.79 77.24256) (xy 166.542235 77.291843) (xy 166.332191 77.432191) (xy 166.191843 77.642235) (xy 166.14256 77.89)
(xy 166.14256 79.59) (xy 166.191843 79.837765) (xy 166.332191 80.047809) (xy 166.542235 80.188157) (xy 166.79 80.23744)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 166.83 80.23744) (xy 166.83 80.724773) (xy 166.830001 80.724778) (xy 166.83 85.010226) (xy 166.814132 85.09)
(xy 166.83 85.169773) (xy 166.876997 85.406045) (xy 167.056023 85.673977) (xy 167.123655 85.719168) (xy 167.645834 86.241347)
(xy 167.691023 86.308977) (xy 167.82227 86.396673) (xy 167.958953 86.488003) (xy 168.275 86.550868) (xy 168.354774 86.535)
(xy 173.654488 86.535) (xy 173.815001 86.695513) (xy 173.815 87.709773) (xy 173.815001 87.709778) (xy 173.815001 87.900299)
(xy 173.726843 88.032235) (xy 173.67756 88.28) (xy 173.67756 90.28) (xy 173.726843 90.527765) (xy 173.867191 90.737809)
(xy 174.077235 90.878157) (xy 174.325 90.92744) (xy 174.925 90.92744) (xy 175.172765 90.878157) (xy 175.26 90.819868)
(xy 175.347235 90.878157) (xy 175.595 90.92744) (xy 176.195 90.92744) (xy 176.442765 90.878157) (xy 176.53 90.819868)
(xy 176.617235 90.878157) (xy 176.865 90.92744) (xy 177.465 90.92744) (xy 177.712765 90.878157) (xy 177.8 90.819868)
(xy 177.887235 90.878157) (xy 178.135 90.92744) (xy 178.735 90.92744) (xy 178.982765 90.878157) (xy 179.07 90.819868)
(xy 179.157235 90.878157) (xy 179.405 90.92744) (xy 180.005 90.92744) (xy 180.252765 90.878157) (xy 180.34 90.819868)
(xy 180.427235 90.878157) (xy 180.675 90.92744) (xy 181.275 90.92744) (xy 181.522765 90.878157) (xy 181.61 90.819868)
(xy 181.697235 90.878157) (xy 181.945 90.92744) (xy 182.545 90.92744) (xy 182.792765 90.878157) (xy 182.88 90.819868)
(xy 182.967235 90.878157) (xy 183.215 90.92744) (xy 183.815 90.92744) (xy 184.062765 90.878157) (xy 184.15 90.819868)
(xy 184.237235 90.878157) (xy 184.485 90.92744) (xy 185.085 90.92744) (xy 185.332765 90.878157) (xy 185.42 90.819868)
(xy 185.507235 90.878157) (xy 185.755 90.92744) (xy 186.355 90.92744) (xy 186.602765 90.878157) (xy 186.69 90.819868)
(xy 186.777235 90.878157) (xy 187.025 90.92744) (xy 187.625 90.92744) (xy 187.872765 90.878157) (xy 187.96 90.819868)
(xy 188.047235 90.878157) (xy 188.295 90.92744) (xy 188.895 90.92744) (xy 189.142765 90.878157) (xy 189.23 90.819868)
(xy 189.317235 90.878157) (xy 189.565 90.92744) (xy 190.165 90.92744) (xy 190.412765 90.878157) (xy 190.5 90.819868)
(xy 190.587235 90.878157) (xy 190.835 90.92744) (xy 191.435 90.92744) (xy 191.682765 90.878157) (xy 191.892809 90.737809)
(xy 192.033157 90.527765) (xy 192.08244 90.28) (xy 192.08244 88.28) (xy 192.033157 88.032235) (xy 191.945 87.9003)
(xy 191.945 59.165806) (xy 218.605612 59.165806) (xy 218.62575 59.915435) (xy 218.873877 60.514467) (xy 219.16668 60.643715)
(xy 220.320395 59.49) (xy 219.16668 58.336285) (xy 218.873877 58.465533) (xy 218.605612 59.165806) (xy 191.945 59.165806)
(xy 191.945 53.88575) (xy 206.21 53.88575) (xy 206.21 55.476309) (xy 206.306673 55.709698) (xy 206.485301 55.888327)
(xy 206.71869 55.985) (xy 207.35925 55.985) (xy 207.518 55.82625) (xy 207.518 53.727) (xy 207.772 53.727)
(xy 207.772 55.82625) (xy 207.93075 55.985) (xy 208.57131 55.985) (xy 208.804699 55.888327) (xy 208.983327 55.709698)
(xy 209.08 55.476309) (xy 209.08 53.88575) (xy 208.92125 53.727) (xy 207.772 53.727) (xy 207.518 53.727)
(xy 206.36875 53.727) (xy 206.21 53.88575) (xy 191.945 53.88575) (xy 191.945 53.040512) (xy 192.740513 52.245)
(xy 196.135227 52.245) (xy 196.215 52.260868) (xy 196.294773 52.245) (xy 196.294774 52.245) (xy 196.531046 52.198003)
(xy 196.798977 52.018977) (xy 196.844168 51.951344) (xy 197.071821 51.723691) (xy 206.21 51.723691) (xy 206.21 53.31425)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 206.36875 53.473) (xy 207.518 53.473) (xy 207.518 51.37375) (xy 207.772 51.37375) (xy 207.772 53.473)
(xy 208.92125 53.473) (xy 209.08 53.31425) (xy 209.08 51.723691) (xy 208.983327 51.490302) (xy 208.804699 51.311673)
(xy 208.57131 51.215) (xy 207.93075 51.215) (xy 207.772 51.37375) (xy 207.518 51.37375) (xy 207.35925 51.215)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 206.71869 51.215) (xy 206.485301 51.311673) (xy 206.306673 51.490302) (xy 206.21 51.723691) (xy 197.071821 51.723691)
(xy 198.001347 50.794166) (xy 198.068977 50.748977) (xy 198.248003 50.481046) (xy 198.295 50.244774) (xy 198.295 50.244773)
(xy 198.310868 50.165001) (xy 198.295 50.085228) (xy 198.295 48.551573) (xy 198.442809 48.452809) (xy 198.583157 48.242765)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 198.63244 47.995) (xy 198.63244 45.485) (xy 198.583157 45.237235) (xy 198.442809 45.027191) (xy 198.232765 44.886843)
(xy 197.985 44.83756) (xy 196.985 44.83756) (xy 196.737235 44.886843) (xy 196.527191 45.027191) (xy 196.386843 45.237235)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 196.33756 45.485) (xy 196.33756 47.995) (xy 196.386843 48.242765) (xy 196.527191 48.452809) (xy 196.675 48.551573)
(xy 196.675 49.829487) (xy 195.879488 50.625) (xy 192.484772 50.625) (xy 192.404999 50.609132) (xy 192.325226 50.625)
(xy 192.088954 50.671997) (xy 191.821023 50.851023) (xy 191.775835 50.918652) (xy 190.618654 52.075834) (xy 190.551024 52.121023)
(xy 190.505836 52.188652) (xy 190.505835 52.188653) (xy 190.5 52.197385) (xy 190.448977 52.121023) (xy 190.381347 52.075834)
(xy 189.405 51.099488) (xy 189.405 48.551573) (xy 189.552809 48.452809) (xy 189.693157 48.242765) (xy 189.74244 47.995)
(xy 189.74244 45.485) (xy 189.693157 45.237235) (xy 189.552809 45.027191) (xy 189.342765 44.886843) (xy 189.095 44.83756)
(xy 188.095 44.83756) (xy 187.847235 44.886843) (xy 187.637191 45.027191) (xy 187.496843 45.237235) (xy 187.44756 45.485)
(xy 187.44756 47.995) (xy 187.496843 48.242765) (xy 187.637191 48.452809) (xy 187.785001 48.551573) (xy 187.785 50.768184)
(xy 187.641046 50.671997) (xy 187.404774 50.625) (xy 187.404773 50.625) (xy 187.325 50.609132) (xy 187.245227 50.625)
(xy 181.310513 50.625) (xy 180.515 49.829488) (xy 180.515 48.551573) (xy 180.662809 48.452809) (xy 180.803157 48.242765)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 180.85244 47.995) (xy 180.85244 45.485) (xy 180.803157 45.237235) (xy 180.662809 45.027191) (xy 180.452765 44.886843)
(xy 180.205 44.83756) (xy 179.205 44.83756) (xy 178.957235 44.886843) (xy 178.747191 45.027191) (xy 178.606843 45.237235)
(xy 178.55756 45.485) (xy 178.55756 47.995) (xy 178.606843 48.242765) (xy 178.747191 48.452809) (xy 178.895001 48.551573)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 178.895001 50.085222) (xy 178.879132 50.165) (xy 178.941998 50.481045) (xy 178.941998 50.481046) (xy 179.121024 50.748977)
(xy 179.188654 50.794166) (xy 180.345834 51.951347) (xy 180.391023 52.018977) (xy 180.658954 52.198003) (xy 180.895226 52.245)
(xy 180.974999 52.260868) (xy 181.054772 52.245) (xy 186.989488 52.245) (xy 187.785 53.040513) (xy 187.785001 83.23)
(xy 187.61075 83.23) (xy 187.452 83.38875) (xy 187.452 84.1755) (xy 187.472 84.1755) (xy 187.472 84.4295)
(xy 187.452 84.4295) (xy 187.452 84.4495) (xy 187.198 84.4495) (xy 187.198 84.4295) (xy 186.37375 84.4295)
(xy 186.215 84.58825) (xy 186.215 84.866309) (xy 186.311673 85.099698) (xy 186.376943 85.164969) (xy 186.268495 85.327273)
(xy 186.20256 85.65875) (xy 186.20256 86.09625) (xy 186.268495 86.427727) (xy 186.456261 86.708739) (xy 186.515 86.747987)
(xy 186.515001 87.664386) (xy 186.355 87.63256) (xy 185.755 87.63256) (xy 185.507235 87.681843) (xy 185.42 87.740132)
(xy 185.332765 87.681843) (xy 185.085 87.63256) (xy 184.485 87.63256) (xy 184.325 87.664386) (xy 184.325 83.738691)
(xy 186.215 83.738691) (xy 186.215 84.01675) (xy 186.37375 84.1755) (xy 187.198 84.1755) (xy 187.198 83.38875)
(xy 187.03925 83.23) (xy 186.72369 83.23) (xy 186.490301 83.326673) (xy 186.311673 83.505302) (xy 186.215 83.738691)
(xy 184.325 83.738691) (xy 184.325 65.620707) (xy 184.392431 65.553276) (xy 184.55 65.17287) (xy 184.55 64.761122)
(xy 184.392431 64.380716) (xy 184.10128 64.089565) (xy 183.720874 63.931996) (xy 183.309126 63.931996) (xy 183.055 64.037258)
(xy 183.055 59.769772) (xy 183.070868 59.689999) (xy 183.045407 59.561997) (xy 183.008003 59.373954) (xy 182.828977 59.106023)
(xy 182.761347 59.060834) (xy 181.644612 57.944099) (xy 181.852431 57.73628) (xy 182.01 57.355874) (xy 182.01 56.944126)
(xy 181.852431 56.56372) (xy 181.56128 56.272569) (xy 181.180874 56.115) (xy 180.769126 56.115) (xy 180.719405 56.135595)
(xy 180.74 56.085874) (xy 180.74 55.674126) (xy 180.582431 55.29372) (xy 180.29128 55.002569) (xy 179.910874 54.845)
(xy 179.815513 54.845) (xy 175.254168 50.283656) (xy 175.208977 50.216023) (xy 174.941046 50.036997) (xy 174.704774 49.99)
(xy 174.704773 49.99) (xy 174.625 49.974132) (xy 174.545227 49.99) (xy 173.563513 49.99) (xy 171.317168 47.743656)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 171.271977 47.676023) (xy 171.004046 47.496997) (xy 170.767774 47.45) (xy 170.767773 47.45) (xy 170.688 47.434132)
(xy 170.608227 47.45) (xy 156.43744 47.45) (xy 156.43744 47.41) (xy 156.388157 47.162235) (xy 156.247809 46.952191)
(xy 156.037765 46.811843) (xy 155.79 46.76256) (xy 154.09 46.76256) (xy 153.842235 46.811843) (xy 153.632191 46.952191)
(xy 153.491843 47.162235) (xy 153.44256 47.41) (xy 153.44256 47.45) (xy 140.884635 47.45) (xy 140.734577 47.225423)
(xy 140.382242 46.99) (xy 140.734577 46.754577) (xy 140.884635 46.53) (xy 141.513888 46.53) (xy 141.698584 46.806416)
(xy 141.987706 46.999602) (xy 142.32875 47.06744) (xy 142.81625 47.06744) (xy 143.157294 46.999602) (xy 143.446416 46.806416)
(xy 143.51 46.711256) (xy 143.573584 46.806416) (xy 143.862706 46.999602) (xy 144.20375 47.06744) (xy 144.69125 47.06744)
(xy 145.032294 46.999602) (xy 145.321416 46.806416) (xy 145.506112 46.53) (xy 147.414513 46.53) (xy 147.453761 46.588739)
(xy 147.734773 46.776505) (xy 148.06625 46.84244) (xy 148.50375 46.84244) (xy 148.835227 46.776505) (xy 149.0725 46.617964)
(xy 149.309773 46.776505) (xy 149.64125 46.84244) (xy 150.07875 46.84244) (xy 150.410227 46.776505) (xy 150.666903 46.605)
(xy 151.831993 46.605) (xy 152.194126 46.755) (xy 152.605874 46.755) (xy 152.98628 46.597431) (xy 153.277431 46.30628)
(xy 153.435 45.925874) (xy 153.435 45.514126) (xy 153.277431 45.13372) (xy 152.98628 44.842569) (xy 152.605874 44.685)
(xy 152.194126 44.685) (xy 151.831993 44.835) (xy 150.666903 44.835) (xy 150.410227 44.663495) (xy 150.07875 44.59756)
(xy 149.64125 44.59756) (xy 149.309773 44.663495) (xy 149.0725 44.822036) (xy 148.835227 44.663495) (xy 148.50375 44.59756)
(xy 148.06625 44.59756) (xy 147.734773 44.663495) (xy 147.453761 44.851261) (xy 147.414513 44.91) (xy 145.506112 44.91)
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 145.321416 44.633584) (xy 145.032294 44.440398) (xy 144.69125 44.37256) (xy 144.20375 44.37256) (xy 143.862706 44.440398)
(xy 143.573584 44.633584) (xy 143.51 44.728744) (xy 143.446416 44.633584) (xy 143.157294 44.440398) (xy 142.81625 44.37256)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 142.32875 44.37256) (xy 141.987706 44.440398) (xy 141.698584 44.633584) (xy 141.513888 44.91) (xy 140.884635 44.91)
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 140.734577 44.685423) (xy 140.259909 44.36826) (xy 139.841333 44.285) (xy 139.558667 44.285) (xy 139.140091 44.36826)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 138.665423 44.685423) (xy 138.557 44.847689) (xy 138.557 42.175) (xy 176.01756 42.175) (xy 176.01756 44.685)
(xy 176.066843 44.932765) (xy 176.207191 45.142809) (xy 176.267196 45.182904) (xy 176.13 45.514126) (xy 176.13 45.925874)
(xy 176.287569 46.30628) (xy 176.57872 46.597431) (xy 176.959126 46.755) (xy 177.370874 46.755) (xy 177.75128 46.597431)
(xy 178.042431 46.30628) (xy 178.2 45.925874) (xy 178.2 45.514126) (xy 178.062804 45.182904) (xy 178.122809 45.142809)
(xy 178.263157 44.932765) (xy 178.31244 44.685) (xy 178.31244 43.71575) (xy 181.11 43.71575) (xy 181.11 44.811309)
(xy 181.206673 45.044698) (xy 181.385301 45.223327) (xy 181.61869 45.32) (xy 181.95925 45.32) (xy 182.118 45.16125)
(xy 182.118 43.557) (xy 182.372 43.557) (xy 182.372 45.16125) (xy 182.53075 45.32) (xy 182.87131 45.32)
(xy 183.104699 45.223327) (xy 183.283327 45.044698) (xy 183.38 44.811309) (xy 183.38 43.71575) (xy 183.22125 43.557)
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add ground and power planes
2018-08-28 21:14:49 +00:00
)
)
)
start pcb layout
2018-08-26 19:54:32 +00:00
)