draw schematic for power latch circuit

This commit is contained in:
interfisch 2021-03-14 17:05:13 +01:00
parent ff35a7dded
commit 1f58d49295
2 changed files with 443 additions and 0 deletions

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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

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EESchema Schematic File Version 4
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Text Notes 3100 1650 0 50 ~ 0
LED for dropping voltage\nfrom 6-8.4v to around 5v
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Text Notes 5900 2100 0 50 ~ 0
0.6V voltage drop\nneeded if battery is full (8.4V)\nvoltage drop of transistor not sufficient
Text Notes 7100 2550 0 50 ~ 0
Output voltage range with 2S LiPo\nwill be good enough for 3v3 reg\non esp8266
Text Notes 1100 1350 0 50 ~ 0
2S LiPo Battery. 6V - 8.4V\nAdditional BMS is recommended
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Debo Touch
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