Merge branch 'p_enable' into constremove
This commit is contained in:
commit
542c46c0c6
86
RF24.cpp
86
RF24.cpp
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@ -28,8 +28,9 @@
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void RF24::csn(int mode) const
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{
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SPI.setBitOrder(MSBFIRST);
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SPI.setDataMode(SPI_MODE0);
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SPI.setClockDivider(SPI_CLOCK_DIV2);
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SPI.setClockDivider(SPI_CLOCK_DIV2);
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digitalWrite(csn_pin,mode);
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}
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@ -212,7 +213,6 @@ RF24::RF24(uint8_t _cepin, uint8_t _cspin):
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ce_pin(_cepin), csn_pin(_cspin), wide_band(true), p_variant(false),
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payload_size(32), ack_payload_available(false)
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{
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begin() ;
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}
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/******************************************************************/
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@ -268,6 +268,14 @@ void RF24::printDetails(void) const
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printf_P(PSTR("RX_ADDR_P3 = 0x%02x"),*buffer);
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printf_P(PSTR("\n\r"));
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status = read_register(RX_ADDR_P4,buffer,1);
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printf_P(PSTR("RX_ADDR_P4 = 0x%02x"),*buffer);
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printf_P(PSTR("\n\r"));
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status = read_register(RX_ADDR_P5,buffer,1);
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printf_P(PSTR("RX_ADDR_P5 = 0x%02x"),*buffer);
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printf_P(PSTR("\n\r"));
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status = read_register(TX_ADDR,buffer,5);
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printf_P(PSTR("TX_ADDR = 0x"));
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bufptr = buffer + 5;
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@ -293,36 +301,52 @@ void RF24::printDetails(void) const
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read_register(RF_SETUP,buffer,1);
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printf_P(PSTR("RF_SETUP = 0x%02x (data rate: %d)\n\r"),*buffer,getDataRate());
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printf_P(PSTR("Hardware; isPVariant: %d\n\r"),isPVariant());
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read_register(CONFIG,buffer,1);
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printf_P(PSTR("CONFIG = 0x%02x (CRC enable: %d; CRC16: %d)\n\r"),
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*buffer,(*buffer)&_BV(EN_CRC)?1:0,
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(*buffer)&_BV(CRCO)?1:0);
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}
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/******************************************************************/
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void RF24::begin(void)
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{
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// Initialize pins
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pinMode(ce_pin,OUTPUT);
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pinMode(csn_pin,OUTPUT);
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// Initialize SPI bus
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// Minimum ideal SPI bus speed is 2x data rate
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// If we assume 2Mbs data rate and 16Mhz clock, a
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// divider of 4 is the minimum we want.
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// CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
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// We'll use a divider of 2 which will work up to
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// MCU speeds of 20Mhz.
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// CLK:BUS 8Mhz:4Mhz, 16Mhz:8Mhz, or 20Mhz:10Mhz (max)
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SPI.begin();
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ce(LOW);
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csn(HIGH);
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SPI.setBitOrder(MSBFIRST);
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SPI.setDataMode(SPI_MODE0);
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SPI.setClockDivider(SPI_CLOCK_DIV2);
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SPI.setClockDivider(SPI_CLOCK_DIV2);
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ce(LOW);
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csn(HIGH);
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// Must allow the radio time to settle else configuration bits will not necessarily stick.
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// This is actually only required following power up but some settling time also appears to
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// be required after resets too. For full coverage, we'll always assume the worst.
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// Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
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// Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
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// WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
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delay( 5 ) ;
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// Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
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// WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
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// sizes must never be used. See documentation for a more complete explanation.
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write_register(SETUP_RETR,(B0100 << ARD) | (B1111 << ARC));
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// Reset current status
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write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
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// Initialize CRC
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write_register(CONFIG, _BV(EN_CRC) );
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// Flush buffers
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flush_rx();
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flush_tx();
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// Restore our default PA level
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setPALevel( RF24_PA_MAX ) ;
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// Determine if this is a p or non-p RF24 module and then
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// reset our data rate back to default value. This works
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@ -332,6 +356,17 @@ void RF24::begin(void)
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p_variant = true ;
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}
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setDataRate( RF24_2MBPS ) ;
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// Initialize CRC and request 2-byte (16bit) CRC
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setCRCLength( RF24_CRC_16 ) ;
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// Reset current status
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// Notice reset and flush is the last thing we do
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write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
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// Flush buffers
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flush_rx();
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flush_tx();
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}
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/******************************************************************/
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@ -788,11 +823,26 @@ rf24_datarate_e RF24::getDataRate( void ) const {
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void RF24::setCRCLength(rf24_crclength_e length) const
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{
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uint8_t config = read_register(CONFIG) & _BV(CRCO);
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if (length == RF24_CRC_16)
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config |= _BV(CRCO);
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write_register(CONFIG,config);
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uint8_t config = read_register(CONFIG) & ~_BV(CRCO) ;
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// Always make sure CRC hardware validation is actually on
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config |= _BV(EN_CRC) ;
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// Now config 8 or 16 bit CRCs - only 16bit need be turned on
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// 8b is the default.
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if( length == RF24_CRC_16 ) {
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config |= _BV( CRCO ) ;
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}
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write_register( CONFIG, config ) ;
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}
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/******************************************************************/
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void RF24::disableCRC( void ) const
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{
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uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ;
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write_register( CONFIG, disable ) ;
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}
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// vim:ai:cin:sts=2 sw=2 ft=cpp
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