2011-03-19 03:32:34 +00:00
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/*
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Copyright (C) 2011 James Coliz, Jr. <maniacbug@ymail.com>
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2011-07-09 05:29:16 +00:00
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2011-03-19 03:32:34 +00:00
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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version 2 as published by the Free Software Foundation.
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*/
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#include <WProgram.h>
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#include <SPI.h>
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#include "RF24.h"
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#include "nRF24L01.h"
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2011-05-11 02:34:22 +00:00
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#undef SERIAL_DEBUG
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2011-03-19 03:32:34 +00:00
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#ifdef SERIAL_DEBUG
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2011-06-30 04:38:17 +00:00
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#define IF_SERIAL_DEBUG(x) ({x;})
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2011-03-19 03:32:34 +00:00
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#else
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#define IF_SERIAL_DEBUG(x)
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#endif
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2011-05-26 03:46:31 +00:00
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// Avoid spurious warnings
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2011-07-09 05:29:16 +00:00
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#undef PROGMEM
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#define PROGMEM __attribute__(( section(".progmem.data") ))
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#undef PSTR
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2011-05-26 03:46:31 +00:00
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#define PSTR(s) (__extension__({static prog_char __c[] PROGMEM = (s); &__c[0];}))
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2011-03-19 03:32:34 +00:00
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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void RF24::csn(int mode)
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2011-03-19 03:32:34 +00:00
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{
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2011-04-24 19:56:43 +00:00
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SPI.setDataMode(SPI_MODE0);
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2011-05-22 06:24:27 +00:00
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SPI.setClockDivider(SPI_CLOCK_DIV8);
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2011-03-19 03:32:34 +00:00
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digitalWrite(csn_pin,mode);
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}
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/******************************************************************/
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void RF24::ce(int mode)
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{
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digitalWrite(ce_pin,mode);
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
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2011-03-19 03:32:34 +00:00
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{
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uint8_t status;
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csn(LOW);
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status = SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
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while ( len-- )
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*buf++ = SPI.transfer(0xff);
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csn(HIGH);
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return status;
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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uint8_t RF24::read_register(uint8_t reg)
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2011-04-30 22:31:04 +00:00
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{
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csn(LOW);
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SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
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uint8_t result = SPI.transfer(0xff);
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csn(HIGH);
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return result;
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}
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/******************************************************************/
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2011-03-19 03:32:34 +00:00
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uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
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{
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uint8_t status;
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csn(LOW);
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status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
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while ( len-- )
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SPI.transfer(*buf++);
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csn(HIGH);
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return status;
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}
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/******************************************************************/
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uint8_t RF24::write_register(uint8_t reg, uint8_t value)
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{
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uint8_t status;
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2011-04-26 03:29:57 +00:00
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IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\n\r"),reg,value));
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2011-03-19 03:32:34 +00:00
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csn(LOW);
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status = SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
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SPI.transfer(value);
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csn(HIGH);
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return status;
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}
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/******************************************************************/
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2011-04-01 04:32:45 +00:00
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uint8_t RF24::write_payload(const void* buf, uint8_t len)
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2011-03-19 03:32:34 +00:00
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{
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uint8_t status;
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2011-06-26 04:24:42 +00:00
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const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
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2011-03-19 03:32:34 +00:00
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csn(LOW);
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status = SPI.transfer( W_TX_PAYLOAD );
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2011-04-01 04:32:45 +00:00
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uint8_t data_len = min(len,payload_size);
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2011-07-10 15:00:58 +00:00
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//uint8_t blank_len = payload_size - data_len;
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2011-04-01 04:32:45 +00:00
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while ( data_len-- )
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2011-03-19 03:32:34 +00:00
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SPI.transfer(*current++);
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2011-07-10 15:00:58 +00:00
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//while ( blank_len-- )
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// SPI.transfer(0);
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2011-03-19 03:32:34 +00:00
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csn(HIGH);
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return status;
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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uint8_t RF24::read_payload(void* buf, uint8_t len)
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2011-03-19 03:32:34 +00:00
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{
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uint8_t status;
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2011-06-26 04:24:42 +00:00
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uint8_t* current = reinterpret_cast<uint8_t*>(buf);
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2011-03-19 03:32:34 +00:00
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csn(LOW);
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status = SPI.transfer( R_RX_PAYLOAD );
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2011-04-01 04:32:45 +00:00
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uint8_t data_len = min(len,payload_size);
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2011-07-10 15:00:58 +00:00
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//uint8_t blank_len = payload_size - data_len;
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2011-04-01 04:32:45 +00:00
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while ( data_len-- )
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2011-03-19 03:32:34 +00:00
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*current++ = SPI.transfer(0xff);
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2011-07-10 15:00:58 +00:00
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//while ( blank_len-- )
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// SPI.transfer(0xff);
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2011-03-19 03:32:34 +00:00
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csn(HIGH);
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return status;
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}
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/******************************************************************/
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uint8_t RF24::flush_rx(void)
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{
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uint8_t status;
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csn(LOW);
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2011-07-09 05:29:16 +00:00
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status = SPI.transfer( FLUSH_RX );
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2011-03-19 03:32:34 +00:00
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csn(HIGH);
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return status;
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}
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/******************************************************************/
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uint8_t RF24::flush_tx(void)
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{
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uint8_t status;
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csn(LOW);
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2011-07-09 05:29:16 +00:00
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status = SPI.transfer( FLUSH_TX );
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2011-03-19 03:32:34 +00:00
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csn(HIGH);
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return status;
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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uint8_t RF24::get_status(void)
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2011-03-19 03:32:34 +00:00
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{
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uint8_t status;
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csn(LOW);
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status = SPI.transfer( NOP );
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csn(HIGH);
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return status;
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}
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/******************************************************************/
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void RF24::print_status(uint8_t status)
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{
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2011-06-28 13:27:36 +00:00
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printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\n\r"),
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2011-07-09 05:29:16 +00:00
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status,
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(status & _BV(RX_DR))?1:0,
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(status & _BV(TX_DS))?1:0,
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(status & _BV(MAX_RT))?1:0,
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((status >> RX_P_NO) & B111),
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(status & _BV(TX_FULL))?1:0
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);
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2011-03-19 03:32:34 +00:00
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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void RF24::print_observe_tx(uint8_t value)
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2011-03-19 03:32:34 +00:00
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{
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2011-04-26 03:40:51 +00:00
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printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\n\r"),
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2011-07-09 05:29:16 +00:00
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value,
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(value >> PLOS_CNT) & B1111,
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(value >> ARC_CNT) & B1111
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);
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2011-03-19 03:32:34 +00:00
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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void RF24::print_byte_register(prog_char* name, uint8_t reg, uint8_t qty)
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2011-06-27 19:54:42 +00:00
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{
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2011-06-28 04:01:58 +00:00
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char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
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2011-06-28 13:27:36 +00:00
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printf_P(PSTR("%S\t%c ="),name,extra_tab);
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while (qty--)
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printf_P(PSTR(" 0x%02x"),read_register(reg++));
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printf_P(PSTR("\n\r"));
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2011-06-27 19:54:42 +00:00
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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void RF24::print_address_register(prog_char* name, uint8_t reg, uint8_t qty)
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2011-06-27 19:54:42 +00:00
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{
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2011-06-28 04:01:58 +00:00
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char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
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2011-06-28 13:27:36 +00:00
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printf_P(PSTR("%S\t%c ="),name,extra_tab);
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2011-07-09 05:29:16 +00:00
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2011-06-28 13:27:36 +00:00
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while (qty--)
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{
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uint8_t buffer[5];
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read_register(reg++,buffer,sizeof buffer);
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printf_P(PSTR(" 0x"));
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uint8_t* bufptr = buffer + sizeof buffer;
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while( --bufptr >= buffer )
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2011-07-09 05:29:16 +00:00
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printf_P(PSTR("%02x"),*bufptr);
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2011-06-28 13:27:36 +00:00
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}
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2011-06-27 19:54:42 +00:00
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printf_P(PSTR("\n\r"));
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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RF24::RF24(uint8_t _cepin, uint8_t _cspin):
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2011-05-10 21:39:01 +00:00
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ce_pin(_cepin), csn_pin(_cspin), payload_size(32), ack_payload_available(false)
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2011-03-19 03:32:34 +00:00
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{
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}
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/******************************************************************/
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2011-04-26 03:29:57 +00:00
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void RF24::setChannel(uint8_t channel)
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2011-03-19 03:32:34 +00:00
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{
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2011-07-09 05:29:16 +00:00
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write_register(RF_CH,min(channel,127));
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2011-03-19 03:32:34 +00:00
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}
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/******************************************************************/
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void RF24::setPayloadSize(uint8_t size)
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{
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payload_size = min(size,32);
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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uint8_t RF24::getPayloadSize(void)
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2011-03-19 03:32:34 +00:00
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{
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return payload_size;
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}
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/******************************************************************/
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2011-07-09 05:29:16 +00:00
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void RF24::printDetails(void)
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2011-03-19 03:32:34 +00:00
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{
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2011-06-27 19:54:42 +00:00
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print_status(get_status());
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2011-06-28 13:27:36 +00:00
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print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
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print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
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2011-06-27 19:54:42 +00:00
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print_address_register(PSTR("TX_ADDR"),TX_ADDR);
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2011-06-28 13:27:36 +00:00
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print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
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2011-06-27 19:54:42 +00:00
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print_byte_register(PSTR("EN_AA"),EN_AA);
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print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
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print_byte_register(PSTR("RF_CH"),RF_CH);
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print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
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2011-06-28 13:30:03 +00:00
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print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
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2011-03-19 03:32:34 +00:00
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}
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/******************************************************************/
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void RF24::begin(void)
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{
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pinMode(ce_pin,OUTPUT);
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pinMode(csn_pin,OUTPUT);
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ce(LOW);
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csn(HIGH);
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SPI.begin();
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SPI.setBitOrder(MSBFIRST);
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SPI.setDataMode(SPI_MODE0);
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SPI.setClockDivider(SPI_CLOCK_DIV8);
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// Set generous timeouts, to make testing a little easier
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write_register(SETUP_RETR,(B1111 << ARD) | (B1111 << ARC));
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// Reset current status
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write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
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2011-07-09 05:29:16 +00:00
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2011-05-28 02:32:59 +00:00
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// Initialize CRC
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write_register(CONFIG, _BV(EN_CRC) );
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2011-03-19 03:32:34 +00:00
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// Flush buffers
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flush_rx();
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2011-07-09 05:29:16 +00:00
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flush_tx();
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2011-03-19 03:32:34 +00:00
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// Set up default configuration. Callers can always change it later.
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setChannel(1);
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}
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/******************************************************************/
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void RF24::startListening(void)
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{
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2011-05-28 02:32:59 +00:00
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write_register(CONFIG, read_register(CONFIG) | _BV(PWR_UP) | _BV(PRIM_RX));
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2011-03-19 03:32:34 +00:00
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write_register(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
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2011-07-09 05:29:16 +00:00
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2011-05-15 14:21:11 +00:00
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// Restore the pipe0 adddress
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|
|
write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&pipe0_reading_address), 5);
|
2011-03-19 03:32:34 +00:00
|
|
|
|
|
|
|
// Flush buffers
|
|
|
|
flush_rx();
|
|
|
|
|
2011-07-09 05:29:16 +00:00
|
|
|
// Go!
|
2011-03-19 03:32:34 +00:00
|
|
|
ce(HIGH);
|
|
|
|
|
|
|
|
// wait for the radio to come up (130us actually only needed)
|
2011-05-26 05:22:21 +00:00
|
|
|
delayMicroseconds(130);
|
2011-03-19 03:32:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
|
|
|
void RF24::stopListening(void)
|
|
|
|
{
|
|
|
|
ce(LOW);
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-05-10 22:16:06 +00:00
|
|
|
void RF24::powerDown(void)
|
|
|
|
{
|
2011-05-28 02:32:59 +00:00
|
|
|
write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP));
|
2011-05-10 22:16:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-04-01 04:32:45 +00:00
|
|
|
boolean RF24::write( const void* buf, uint8_t len )
|
2011-03-19 03:32:34 +00:00
|
|
|
{
|
|
|
|
boolean result = false;
|
|
|
|
|
2011-07-07 03:49:59 +00:00
|
|
|
// Begin the write
|
|
|
|
startWrite(buf,len);
|
2011-06-30 04:38:17 +00:00
|
|
|
|
|
|
|
// ------------
|
|
|
|
// At this point we could return from a non-blocking write, and then call
|
|
|
|
// the rest after an interrupt
|
|
|
|
|
|
|
|
// Instead, we are going to block here until we get TX_DS (transmission completed and ack'd)
|
|
|
|
// or MAX_RT (maximum retries, transmission failed). Also, we'll timeout in case the radio
|
|
|
|
// is flaky and we get neither.
|
2011-03-19 03:32:34 +00:00
|
|
|
|
|
|
|
uint8_t observe_tx;
|
|
|
|
uint8_t status;
|
2011-06-30 04:38:17 +00:00
|
|
|
uint32_t sent_at = millis();
|
2011-07-09 05:29:16 +00:00
|
|
|
const uint32_t timeout = 500; //ms to wait for timeout
|
2011-03-19 03:32:34 +00:00
|
|
|
do
|
|
|
|
{
|
|
|
|
status = read_register(OBSERVE_TX,&observe_tx,1);
|
|
|
|
IF_SERIAL_DEBUG(Serial.print(observe_tx,HEX));
|
|
|
|
}
|
2011-06-30 04:38:17 +00:00
|
|
|
while( ! ( status & ( _BV(TX_DS) | _BV(MAX_RT) ) ) && ( millis() - sent_at < timeout ) );
|
2011-03-19 03:32:34 +00:00
|
|
|
|
2011-06-30 04:46:46 +00:00
|
|
|
// The part above is what you could recreate with your own interrupt handler,
|
|
|
|
// and then call this when you got an interrupt
|
|
|
|
// ------------
|
|
|
|
|
2011-07-07 02:51:30 +00:00
|
|
|
// Call this when you get an interrupt
|
2011-06-30 04:46:46 +00:00
|
|
|
// The status tells us three things
|
|
|
|
// * The send was successful (TX_DS)
|
|
|
|
// * The send failed, too many retries (MAX_RT)
|
|
|
|
// * There is an ack packet waiting (RX_DR)
|
2011-07-07 02:51:30 +00:00
|
|
|
bool tx_ok, tx_fail, ack_payload_available;
|
|
|
|
whatHappened(tx_ok,tx_fail,ack_payload_available);
|
2011-06-30 04:46:46 +00:00
|
|
|
|
2011-07-07 02:51:30 +00:00
|
|
|
result = tx_ok;
|
|
|
|
IF_SERIAL_DEBUG(Serial.print(result?"...OK.":"...Failed"));
|
2011-06-30 04:38:17 +00:00
|
|
|
|
2011-06-30 04:46:46 +00:00
|
|
|
// Handle the ack packet
|
2011-05-10 21:39:01 +00:00
|
|
|
if ( ack_payload_available )
|
2011-04-30 22:31:04 +00:00
|
|
|
{
|
2011-07-10 15:00:58 +00:00
|
|
|
ack_payload_length = getDynamicPayloadSize();
|
2011-04-30 22:31:04 +00:00
|
|
|
IF_SERIAL_DEBUG(Serial.print("[AckPacket]/"));
|
2011-05-10 21:39:01 +00:00
|
|
|
IF_SERIAL_DEBUG(Serial.println(ack_payload_length,DEC));
|
2011-04-30 22:31:04 +00:00
|
|
|
}
|
2011-03-19 03:32:34 +00:00
|
|
|
|
|
|
|
// Yay, we are done.
|
|
|
|
|
|
|
|
// Power down
|
2011-06-30 04:46:46 +00:00
|
|
|
powerDown();
|
2011-03-19 03:32:34 +00:00
|
|
|
|
2011-06-30 04:46:46 +00:00
|
|
|
// Flush buffers (Is this a relic of past experimentation, and not needed anymore??)
|
2011-07-09 05:29:16 +00:00
|
|
|
flush_tx();
|
2011-03-19 03:32:34 +00:00
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
2011-07-07 03:49:59 +00:00
|
|
|
/******************************************************************/
|
|
|
|
|
|
|
|
void RF24::startWrite( const void* buf, uint8_t len )
|
|
|
|
{
|
|
|
|
// Transmitter power-up
|
|
|
|
write_register(CONFIG, ( read_register(CONFIG) | _BV(PWR_UP) ) & ~_BV(PRIM_RX) );
|
|
|
|
delay(2);
|
|
|
|
|
|
|
|
// Send the payload
|
|
|
|
write_payload( buf, len );
|
|
|
|
|
|
|
|
// Allons!
|
|
|
|
ce(HIGH);
|
|
|
|
delayMicroseconds(15);
|
|
|
|
ce(LOW);
|
|
|
|
}
|
2011-05-10 21:39:01 +00:00
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-07-10 15:00:58 +00:00
|
|
|
uint8_t RF24::getDynamicPayloadSize(void)
|
2011-05-10 21:39:01 +00:00
|
|
|
{
|
|
|
|
uint8_t result = 0;
|
|
|
|
|
|
|
|
csn(LOW);
|
|
|
|
SPI.transfer( R_RX_PL_WID );
|
|
|
|
result = SPI.transfer(0xff);
|
|
|
|
csn(HIGH);
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2011-03-19 03:32:34 +00:00
|
|
|
/******************************************************************/
|
|
|
|
|
2011-07-09 05:29:16 +00:00
|
|
|
boolean RF24::available(void)
|
2011-04-02 05:55:33 +00:00
|
|
|
{
|
|
|
|
return available(NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-07-09 05:29:16 +00:00
|
|
|
boolean RF24::available(uint8_t* pipe_num)
|
2011-03-19 03:32:34 +00:00
|
|
|
{
|
|
|
|
uint8_t status = get_status();
|
2011-06-30 04:38:17 +00:00
|
|
|
|
|
|
|
// Too noisy, enable if you really want lots o data!! IF_SERIAL_DEBUG(print_status(status));
|
2011-07-09 05:29:16 +00:00
|
|
|
|
2011-03-19 03:32:34 +00:00
|
|
|
boolean result = ( status & _BV(RX_DR) );
|
|
|
|
|
|
|
|
if (result)
|
|
|
|
{
|
2011-04-02 05:55:33 +00:00
|
|
|
// If the caller wants the pipe number, include that
|
|
|
|
if ( pipe_num )
|
|
|
|
*pipe_num = ( status >> RX_P_NO ) & B111;
|
|
|
|
|
2011-03-19 03:32:34 +00:00
|
|
|
// Clear the status bit
|
2011-04-02 05:55:33 +00:00
|
|
|
|
|
|
|
// ??? Should this REALLY be cleared now? Or wait until we
|
|
|
|
// actually READ the payload?
|
|
|
|
|
2011-03-19 03:32:34 +00:00
|
|
|
write_register(STATUS,_BV(RX_DR) );
|
2011-04-30 22:31:04 +00:00
|
|
|
|
|
|
|
// Handle ack payload receipt
|
|
|
|
if ( status & _BV(TX_DS) )
|
|
|
|
{
|
|
|
|
write_register(STATUS,_BV(TX_DS));
|
|
|
|
}
|
2011-03-19 03:32:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-07-09 05:29:16 +00:00
|
|
|
boolean RF24::read( void* buf, uint8_t len )
|
2011-03-19 03:32:34 +00:00
|
|
|
{
|
|
|
|
// Fetch the payload
|
2011-04-01 04:32:45 +00:00
|
|
|
read_payload( buf, len );
|
2011-03-19 03:32:34 +00:00
|
|
|
|
2011-07-10 15:12:12 +00:00
|
|
|
// was this the last of the data available?
|
|
|
|
return read_register(FIFO_STATUS) & _BV(RX_EMPTY);
|
2011-03-19 03:32:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-07-07 02:51:30 +00:00
|
|
|
void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
|
|
|
|
{
|
2011-07-09 05:29:16 +00:00
|
|
|
// Read the status & reset the status in one easy call
|
2011-07-09 05:25:44 +00:00
|
|
|
uint8_t status = write_register(STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
|
2011-07-07 02:51:30 +00:00
|
|
|
|
|
|
|
// Report to the user what happened
|
|
|
|
tx_ok = status & _BV(TX_DS);
|
|
|
|
tx_fail = status & _BV(MAX_RT);
|
|
|
|
rx_ready = status & _BV(RX_DR);
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-03-19 03:32:34 +00:00
|
|
|
void RF24::openWritingPipe(uint64_t value)
|
|
|
|
{
|
|
|
|
// Note that AVR 8-bit uC's store this LSB first, and the NRF24L01
|
2011-07-09 05:29:16 +00:00
|
|
|
// expects it LSB first too, so we're good.
|
|
|
|
|
2011-03-19 03:32:34 +00:00
|
|
|
write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), 5);
|
2011-07-09 05:29:16 +00:00
|
|
|
write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), 5);
|
2011-04-01 04:32:45 +00:00
|
|
|
write_register(RX_PW_P0,min(payload_size,32));
|
2011-03-19 03:32:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
|
|
|
void RF24::openReadingPipe(uint8_t child, uint64_t value)
|
|
|
|
{
|
2011-07-09 05:29:16 +00:00
|
|
|
const uint8_t child_pipe[] =
|
|
|
|
{
|
|
|
|
RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
|
|
|
|
};
|
|
|
|
const uint8_t child_payload_size[] =
|
|
|
|
{
|
|
|
|
RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
|
|
|
|
};
|
|
|
|
const uint8_t child_pipe_enable[] =
|
|
|
|
{
|
|
|
|
ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
|
|
|
|
};
|
2011-03-19 03:32:34 +00:00
|
|
|
|
2011-05-15 14:21:11 +00:00
|
|
|
// If this is pipe 0, cache the address. This is needed because
|
|
|
|
// openWritingPipe() will overwrite the pipe 0 address, so
|
|
|
|
// startListening() will have to restore it.
|
|
|
|
if (child == 0)
|
|
|
|
pipe0_reading_address = value;
|
|
|
|
|
2011-06-26 04:18:13 +00:00
|
|
|
if (child <= 5)
|
2011-03-19 03:32:34 +00:00
|
|
|
{
|
2011-04-02 05:55:33 +00:00
|
|
|
// For pipes 2-5, only write the LSB
|
2011-05-13 04:46:27 +00:00
|
|
|
if ( child < 2 )
|
2011-07-09 05:29:16 +00:00
|
|
|
write_register(child_pipe[child], reinterpret_cast<uint8_t*>(&value), 5);
|
|
|
|
else
|
|
|
|
write_register(child_pipe[child], reinterpret_cast<uint8_t*>(&value), 1);
|
|
|
|
|
|
|
|
write_register(child_payload_size[child],payload_size);
|
2011-03-19 03:32:34 +00:00
|
|
|
|
2011-06-28 13:56:24 +00:00
|
|
|
// Note it would be more efficient to set all of the bits for all open
|
|
|
|
// pipes at once. However, I thought it would make the calling code
|
|
|
|
// more simple to do it this way.
|
|
|
|
write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(child_pipe_enable[child]));
|
2011-03-19 03:32:34 +00:00
|
|
|
}
|
|
|
|
}
|
2011-04-30 22:31:04 +00:00
|
|
|
|
|
|
|
/******************************************************************/
|
2011-07-09 05:29:16 +00:00
|
|
|
|
2011-04-30 22:31:04 +00:00
|
|
|
void RF24::toggle_features(void)
|
|
|
|
{
|
|
|
|
csn(LOW);
|
|
|
|
SPI.transfer( ACTIVATE );
|
|
|
|
SPI.transfer( 0x73 );
|
|
|
|
csn(HIGH);
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-07-10 15:00:58 +00:00
|
|
|
void RF24::enableDynamicPayloads(void)
|
|
|
|
{
|
|
|
|
// Enable dynamic payload throughout the system
|
|
|
|
write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
|
|
|
|
|
|
|
|
// If it didn't work, the features are not enabled
|
|
|
|
if ( ! read_register(FEATURE) )
|
|
|
|
{
|
|
|
|
// So enable them and try again
|
|
|
|
toggle_features();
|
|
|
|
write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
|
|
|
|
}
|
|
|
|
|
|
|
|
IF_SERIAL_DEBUG(printf("FEATURE=%i\n\r",read_register(FEATURE)));
|
|
|
|
|
|
|
|
// Enable dynamic payload on all pipes
|
|
|
|
//
|
|
|
|
// Not sure the use case of only having dynamic payload on certain
|
|
|
|
// pipes, so the library does not support it.
|
|
|
|
write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
2011-04-30 22:31:04 +00:00
|
|
|
void RF24::enableAckPayload(void)
|
|
|
|
{
|
|
|
|
//
|
|
|
|
// enable ack payload and dynamic payload features
|
|
|
|
//
|
|
|
|
|
|
|
|
write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
|
|
|
|
|
|
|
|
// If it didn't work, the features are not enabled
|
|
|
|
if ( ! read_register(FEATURE) )
|
|
|
|
{
|
|
|
|
// So enable them and try again
|
|
|
|
toggle_features();
|
|
|
|
write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
|
|
|
|
}
|
|
|
|
|
|
|
|
IF_SERIAL_DEBUG(printf("FEATURE=%i\n\r",read_register(FEATURE)));
|
|
|
|
|
|
|
|
//
|
2011-07-10 15:00:58 +00:00
|
|
|
// Enable dynamic payload on pipes 0 & 1
|
2011-04-30 22:31:04 +00:00
|
|
|
//
|
|
|
|
|
|
|
|
write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
|
|
|
void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
|
|
|
|
{
|
2011-06-26 04:24:42 +00:00
|
|
|
const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
|
2011-04-30 22:31:04 +00:00
|
|
|
|
|
|
|
csn(LOW);
|
|
|
|
SPI.transfer( W_ACK_PAYLOAD | ( pipe & B111 ) );
|
|
|
|
uint8_t data_len = min(len,32);
|
|
|
|
while ( data_len-- )
|
|
|
|
SPI.transfer(*current++);
|
|
|
|
|
|
|
|
csn(HIGH);
|
|
|
|
}
|
|
|
|
|
|
|
|
/******************************************************************/
|
|
|
|
|
|
|
|
boolean RF24::isAckPayloadAvailable(void)
|
|
|
|
{
|
2011-05-10 21:39:01 +00:00
|
|
|
boolean result = ack_payload_available;
|
|
|
|
ack_payload_available = false;
|
2011-04-30 22:31:04 +00:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2011-05-26 05:22:21 +00:00
|
|
|
/******************************************************************/
|
|
|
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void RF24::setAutoAck(bool enable)
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{
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if ( enable )
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write_register(EN_AA, B111111);
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else
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write_register(EN_AA, 0);
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}
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/******************************************************************/
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boolean RF24::testCarrier(void)
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{
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return ( read_register(CD) & 1 );
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}
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2011-05-27 03:48:30 +00:00
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/******************************************************************/
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void RF24::setDataRate(rf24_datarate_e speed)
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{
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2011-06-28 13:46:45 +00:00
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uint8_t setup = read_register(RF_SETUP) & _BV(RF_DR);
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2011-05-27 03:48:30 +00:00
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if (speed == RF24_2MBPS)
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2011-05-28 03:11:38 +00:00
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setup |= _BV(RF_DR);
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2011-05-27 03:48:30 +00:00
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write_register(RF_SETUP,setup);
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2011-05-28 03:09:29 +00:00
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}
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/******************************************************************/
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void RF24::setCRCLength(rf24_crclength_e length)
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|
{
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|
uint8_t config = read_register(CONFIG) & _BV(CRCO);
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if (length == RF24_CRC_16)
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config |= _BV(CRCO);
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|
write_register(CONFIG,config);
|
2011-05-27 03:48:30 +00:00
|
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}
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|
2011-06-28 13:44:41 +00:00
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/******************************************************************/
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void RF24::setRetries(uint8_t delay, uint8_t count)
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|
|
{
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|
|
write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
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}
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|
2011-04-24 18:24:21 +00:00
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// vim:ai:cin:sts=2 sw=2 ft=cpp
|
2011-04-02 05:55:33 +00:00
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