4 Commits

Author	SHA1	Message	Date
interfisch	7deb5b6e60	design finished	2023-10-11 18:18:22 +02:00
interfisch	623a4e731e	some routing done	2023-09-27 21:50:46 +02:00
interfisch	c1813fff5f	rough placement of components	2023-09-27 20:29:57 +02:00
interfisch	0d2101549b	draw current state of row driver board	2023-02-04 00:19:25 +01:00