From f7f963167cdc1d78aee6137275053155bd6986e0 Mon Sep 17 00:00:00 2001 From: Fisch Date: Sat, 1 Feb 2020 01:04:57 +0100 Subject: [PATCH] fix missing gnd flag --- reverseengeneering/annax37623/annax37623.bak | 18 ++++++++---------- reverseengeneering/annax37623/annax37623.sch | 2 ++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/reverseengeneering/annax37623/annax37623.bak b/reverseengeneering/annax37623/annax37623.bak index f389193..fca4347 100644 --- a/reverseengeneering/annax37623/annax37623.bak +++ b/reverseengeneering/annax37623/annax37623.bak @@ -1105,12 +1105,6 @@ F 3 "" H 4450 3000 50 0001 C CNN $EndComp Wire Wire Line 4450 3000 4450 2900 -Wire Wire Line - 7050 4550 7050 4650 -Wire Wire Line - 7050 4650 7100 4650 -Wire Wire Line - 5150 2700 4950 2700 NoConn ~ 2700 2150 $Comp L 4xxx_IEEE:4015 USR1 @@ -1472,8 +1466,6 @@ Text GLabel 11600 9600 0 50 Input ~ 0 Clock Text GLabel 5400 8500 0 50 Input ~ 0 Clock -Text GLabel 5150 2700 2 50 Input ~ 0 -Clock Wire Wire Line 9850 6800 10050 6800 Wire Wire Line @@ -3836,8 +3828,6 @@ Wire Wire Line 12250 3500 12250 3550 Wire Wire Line 6600 3050 11150 3050 -Text GLabel 7100 4650 2 50 Input ~ 0 -Clock Wire Wire Line 4000 4500 6400 4500 Wire Wire Line @@ -3914,4 +3904,12 @@ Wire Wire Line Connection ~ 4350 2700 Text GLabel 5150 2900 2 50 Input ~ 0 Clock +Wire Wire Line + 7200 2700 7200 4600 +Wire Wire Line + 7200 4600 7050 4600 +Wire Wire Line + 7050 4600 7050 4550 +Wire Wire Line + 4950 2700 7200 2700 $EndSCHEMATC diff --git a/reverseengeneering/annax37623/annax37623.sch b/reverseengeneering/annax37623/annax37623.sch index fca4347..f89fea9 100644 --- a/reverseengeneering/annax37623/annax37623.sch +++ b/reverseengeneering/annax37623/annax37623.sch @@ -3912,4 +3912,6 @@ Wire Wire Line 7050 4600 7050 4550 Wire Wire Line 4950 2700 7200 2700 +Text Notes 3500 3600 2 50 ~ 0 +GND $EndSCHEMATC