From c1813fff5fa1287df054b4b8c007070a83a02bbf Mon Sep 17 00:00:00 2001 From: Fisch Date: Wed, 27 Sep 2023 20:29:57 +0200 Subject: [PATCH] rough placement of components --- .../driverboardAnnax37623.kicad_pcb | 4204 ++++++++++++++++- .../driverboardAnnax37623.kicad_prl | 2 +- 2 files changed, 4204 insertions(+), 2 deletions(-) diff --git a/driverboardAnnax37623/driverboardAnnax37623.kicad_pcb b/driverboardAnnax37623/driverboardAnnax37623.kicad_pcb index 28b47a1..bad38db 100644 --- a/driverboardAnnax37623/driverboardAnnax37623.kicad_pcb +++ b/driverboardAnnax37623/driverboardAnnax37623.kicad_pcb @@ -1,2 +1,4204 @@ (kicad_pcb (version 20211014) (generator pcbnew) -) \ No newline at end of file + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (pad_to_mask_clearance 0) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (svguseinch false) + (svgprecision 6) + (excludeedgelayer true) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + (net 1 "Net-(C1-Pad1)") + (net 2 "GNDD") + (net 3 "Net-(C2-Pad1)") + (net 4 "VCC") + (net 5 "+3V3") + (net 6 "+12V") + (net 7 "Vdrive") + (net 8 "Clear") + (net 9 "Vin") + (net 10 "Vflipdot") + (net 11 "sr_data") + (net 12 "sr_clk") + (net 13 "sr_latch") + (net 14 "sr_oe") + (net 15 "Net-(J2-Pad5)") + (net 16 "Y0") + (net 17 "Y1") + (net 18 "Y2") + (net 19 "Y3") + (net 20 "Y4") + (net 21 "Y5") + (net 22 "Y6") + (net 23 "Y7") + (net 24 "Y8") + (net 25 "Y9") + (net 26 "YA") + (net 27 "YB") + (net 28 "YC") + (net 29 "YD") + (net 30 "YE") + (net 31 "YF") + (net 32 "GNDPWR") + (net 33 "data") + (net 34 "reset") + (net 35 "clock") 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