229 lines
8.0 KiB
C
229 lines
8.0 KiB
C
/**************************************************************************/
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/*!
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@file adc.c
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@author K. Townsend (microBuilder.eu)
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@date 22 March 2010
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@version 0.10
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@section Description
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SW-based single-channel A/D conversion. If you wish to convert
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multiple ADC channels simultaneously, this code will need to be
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modified to work in BURST mode.
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@section Example
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@code
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#include "core/cpu/cpu.h"
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#include "core/adc/adc.h"
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void main (void)
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{
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cpuInit();
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adcInit();
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uint32_t results = 0;
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while(1)
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{
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// Get A/D conversion results from A/D channel 0
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results = adcRead(0);
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}
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}
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@endcode
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2010, microBuilder SARL
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**************************************************************************/
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#include "adc.h"
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static bool _adcInitialised = false;
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static uint8_t _adcLastChannel = 0;
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/**************************************************************************/
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/*!
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@brief Returns the conversion results on the specified ADC channel.
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This function will manually start an A/D conversion on a single
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channel and return the results.
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@param[in] channelNum
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The A/D channel [0..7] that will be used during the A/D
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conversion. (Note that only A/D channel's 0..3 are
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configured by default in adcInit.)
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@return 0 if an overrun error occured, otherwise a 10-bit value
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containing the A/D conversion results.
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@warning Only AD channels 0..3 are configured for A/D in adcInit.
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If you wish to use A/D pins 4..7 they will also need to
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be added to the adcInit function.
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*/
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/**************************************************************************/
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uint32_t adcRead (uint8_t channelNum)
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{
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if (!_adcInitialised) adcInit();
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uint32_t regVal, adcData;
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/* make sure that channel number is 0..7 */
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if ( channelNum >= 8 )
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{
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// ToDo: Change this to throw an exception back
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channelNum = 0;
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}
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/* Deselect all channels */
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ADC_AD0CR &= ~ADC_AD0CR_SEL_MASK;
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/* Start converting now on the appropriate channel */
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ADC_AD0CR |= ADC_AD0CR_START_STARTNOW | (1 << channelNum);
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/* wait until end of A/D convert */
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while ( 1 )
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{
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// Get data register results for the requested channel
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switch (channelNum)
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{
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case 0:
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regVal = (*(pREG32(ADC_AD0DR0)));
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break;
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case 1:
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regVal = (*(pREG32(ADC_AD0DR1)));
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break;
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case 2:
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regVal = (*(pREG32(ADC_AD0DR2)));
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break;
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case 3:
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regVal = (*(pREG32(ADC_AD0DR3)));
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break;
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case 4:
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regVal = (*(pREG32(ADC_AD0DR4)));
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break;
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case 5:
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regVal = (*(pREG32(ADC_AD0DR5)));
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break;
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case 6:
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regVal = (*(pREG32(ADC_AD0DR6)));
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break;
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case 7:
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regVal = (*(pREG32(ADC_AD0DR7)));
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break;
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default:
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regVal = (*(pREG32(ADC_AD0DR0)));
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break;
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}
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/* read result of A/D conversion */
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if (regVal & ADC_DR_DONE)
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{
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break;
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}
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}
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/* stop ADC */
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ADC_AD0CR &= ~ADC_AD0CR_START_MASK;
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/* return 0 if an overrun occurred */
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if ( regVal & ADC_DR_OVERRUN )
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{
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return (1);
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}
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/* return conversion results */
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adcData = (regVal >> 6) & 0x3FF;
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return (adcData);
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}
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/**************************************************************************/
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/*!
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@brief Initialises the A/D converter and configures channels 0..3
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for 10-bit, SW-controlled A/D conversion.
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@return Nothing
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*/
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/**************************************************************************/
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void adcInit (void)
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{
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/* Disable Power down bit to the ADC block. */
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SCB_PDRUNCFG &= ~(SCB_PDRUNCFG_ADC);
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/* Enable AHB clock to the ADC. */
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SCB_SYSAHBCLKCTRL |= (SCB_SYSAHBCLKCTRL_ADC);
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/* Digital pins need to have the 'analog' bit set in addition
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to changing their pin function */
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/* Set AD0 to analog input */
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IOCON_JTAG_TDI_PIO0_11 &= ~(IOCON_JTAG_TDI_PIO0_11_ADMODE_MASK |
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IOCON_JTAG_TDI_PIO0_11_FUNC_MASK |
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IOCON_JTAG_TDI_PIO0_11_MODE_MASK);
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IOCON_JTAG_TDI_PIO0_11 |= (IOCON_JTAG_TDI_PIO0_11_FUNC_AD0 &
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IOCON_JTAG_TDI_PIO0_11_ADMODE_ANALOG);
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/* Set AD1 to analog input */
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IOCON_JTAG_TMS_PIO1_0 &= ~(IOCON_JTAG_TMS_PIO1_0_ADMODE_MASK |
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IOCON_JTAG_TMS_PIO1_0_FUNC_MASK |
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IOCON_JTAG_TMS_PIO1_0_MODE_MASK);
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IOCON_JTAG_TMS_PIO1_0 |= (IOCON_JTAG_TMS_PIO1_0_FUNC_AD1 &
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IOCON_JTAG_TMS_PIO1_0_ADMODE_ANALOG);
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/* Set AD2 to analog input */
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IOCON_JTAG_TDO_PIO1_1 &= ~(IOCON_JTAG_TDO_PIO1_1_ADMODE_MASK |
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IOCON_JTAG_TDO_PIO1_1_FUNC_MASK |
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IOCON_JTAG_TDO_PIO1_1_MODE_MASK);
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IOCON_JTAG_TDO_PIO1_1 |= (IOCON_JTAG_TDO_PIO1_1_FUNC_AD2 &
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IOCON_JTAG_TDO_PIO1_1_ADMODE_ANALOG);
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/* Set AD3 to analog input */
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IOCON_JTAG_nTRST_PIO1_2 &= ~(IOCON_JTAG_nTRST_PIO1_2_ADMODE_MASK |
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IOCON_JTAG_nTRST_PIO1_2_FUNC_MASK |
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IOCON_JTAG_nTRST_PIO1_2_MODE_MASK);
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IOCON_JTAG_nTRST_PIO1_2 |= (IOCON_JTAG_nTRST_PIO1_2_FUNC_AD3 &
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IOCON_JTAG_nTRST_PIO1_2_ADMODE_ANALOG);
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/* Note that in SW mode only one channel can be selected at a time (AD0 in this case)
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To select multiple channels, ADC_AD0CR_BURST_HWSCANMODE must be used */
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ADC_AD0CR = (ADC_AD0CR_SEL_AD0 | /* SEL=1,select channel 0 on ADC0 */
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(((CFG_CPU_CCLK / SCB_SYSAHBCLKDIV) / 1000000 - 1 ) << 8) | /* CLKDIV = Fpclk / 1000000 - 1 */
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ADC_AD0CR_BURST_SWMODE | /* BURST = 0, no BURST, software controlled */
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ADC_AD0CR_CLKS_10BITS | /* CLKS = 0, 11 clocks/10 bits */
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ADC_AD0CR_START_NOSTART | /* START = 0 A/D conversion stops */
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ADC_AD0CR_EDGE_RISING); /* EDGE = 0 (CAP/MAT signal falling, trigger A/D conversion) */
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/* Set initialisation flag */
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_adcInitialised = true;
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/* Set last channel flag to 0 (initialised above) */
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_adcLastChannel = 0;
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return;
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}
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