122 lines
3.3 KiB
C
122 lines
3.3 KiB
C
#ifndef _NRF24L01P_H
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#define _NRF24L01P_H 1
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#define MAX_PKT (32-2) // 2 bytes are our CRC
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// SPI commands
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#define C_R_REGISTER 0x00
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#define C_W_REGISTER 0x20
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#define C_R_RX_PAYLOAD 0x61
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#define C_W_TX_PAYLOAD 0xA0
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#define C_FLUSH_TX 0xE1
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#define C_FLUSH_RX 0xE2
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#define C_REUSE_TX_PL 0xE3
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#define C_R_RX_PL_WID 0x60
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#define C_W_ACK_PAYLOAD 0xA8
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#define C_W_TX_PAYLOAD_NOCACK 0xB0
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#define C_NOP 0xFF
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// Registers
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#define R_CONFIG 0x00
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#define R_EN_AA 0x01
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#define R_EN_RXADDR 0x02
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#define R_SETUP_AW 0x03
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#define R_SETUP_RETR 0x04
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#define R_RF_CH 0x05
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#define R_RF_SETUP 0x06
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#define R_STATUS 0x07
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#define R_OBSERVE_TX 0x08
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#define R_RPD 0x09
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#define R_RX_ADDR_P0 0x0A
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#define R_RX_ADDR_P0_LEN 5
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#define R_RX_ADDR_P1 0x0B
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#define R_RX_ADDR_P1_LEN 5
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#define R_RX_ADDR_P2 0x0C
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#define R_RX_ADDR_P2_LEN 1
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#define R_RX_ADDR_P3 0x0D
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#define R_RX_ADDR_P3_LEN 1
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#define R_RX_ADDR_P4 0x0E
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#define R_RX_ADDR_P4_LEN 1
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#define R_RX_ADDR_P5 0x0F
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#define R_RX_ADDR_P5_LEN 1
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#define R_TX_ADDR 0x10
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#define R_TX_ADDR_LEN 5
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#define R_RX_PW_P0 0x11
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#define R_RX_PW_P1 0x12
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#define R_RX_PW_P2 0x13
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#define R_RX_PW_P3 0x14
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#define R_RX_PW_P4 0x15
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#define R_RX_PW_P5 0x16
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#define R_FIFO_STATUS 0x17
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#define R_DYNPD 0x1c
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// Register Flags
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//CONFIG register definitions
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#define R_CONFIG_RESERVED 0x80
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#define R_CONFIG_MASK_RX_DR 0x40
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#define R_CONFIG_MASK_TX_DS 0x20
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#define R_CONFIG_MASK_MAX_RT 0x10
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#define R_CONFIG_EN_CRC 0x08
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#define R_CONFIG_CRCO 0x04
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#define R_CONFIG_PWR_UP 0x02
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#define R_CONFIG_PRIM_RX 0x01
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//EN_AA register definitions
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#define R_EN_AA_ENAA_P5 0x20
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#define R_EN_AA_ENAA_P4 0x10
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#define R_EN_AA_ENAA_P3 0x08
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#define R_EN_AA_ENAA_P2 0x04
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#define R_EN_AA_ENAA_P1 0x02
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#define R_EN_AA_ENAA_P0 0x01
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#define R_EN_AA_ENAA_NONE 0x00
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//EN_RXADDR register definitions
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#define R_EN_RXADDR_ERX_P5 0x20
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#define R_EN_RXADDR_ERX_P4 0x10
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#define R_EN_RXADDR_ERX_P3 0x08
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#define R_EN_RXADDR_ERX_P2 0x04
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#define R_EN_RXADDR_ERX_P1 0x02
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#define R_EN_RXADDR_ERX_P0 0x01
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#define R_EN_RXADDR_ERX_NONE 0x00
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//RF_SETUP register definitions
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#define R_RF_CONT_WAVE 0x80
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#define R_RF_SETUP_RF_DR_LOW 0x20
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#define R_RF_SETUP_PLL_LOCK 0x10
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#define R_RF_SETUP_RF_DR_HIGH 0x08
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#define R_RF_SETUP_RF_PWR_0 0x00
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#define R_RF_SETUP_RF_PWR_1 0x02
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#define R_RF_SETUP_RF_PWR_2 0x04
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#define R_RF_SETUP_RF_PWR_3 0x06
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#define R_RF_SETUP_DR_1M 0x00
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#define R_RF_SETUP_DR_2M 0x08
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#define R_RF_SETUP_DR_250K 0x20
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//STATUS register definitions
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#define R_STATUS_RX_DR 0x40
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#define R_STATUS_TX_DS 0x20
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#define R_STATUS_MAX_RT 0x10
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#define R_STATUS_RX_P_NO 0x0E
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#define R_STATUS_GET_RX_P_NO(x) ((x&R_STATUS_RX_P_NO)>>1)
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#define R_STATUS_RX_FIFO_EMPTY 0x0E
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#define R_STATUS_TX_FULL 0x01
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/* exported functions */
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int nrf_rcv_pkt_time(int maxtime, int maxsize, uint8_t * pkt);
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void nrf_init() ;
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void nrf_cmd(uint8_t cmd);
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uint8_t nrf_cmd_status(uint8_t cmd);
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void nrf_cmd_rw_long(uint8_t* data, int len);
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void nrf_read_long(const uint8_t reg, int len, uint8_t* data);
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void nrf_write_reg(const uint8_t reg, const uint8_t val);
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void nrf_write_reg_long(const uint8_t reg, int len, uint8_t* data);
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/* END */
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#endif /* _NRF24L01P_H */
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