437 lines
11 KiB
C
437 lines
11 KiB
C
#include <basic/basic.h>
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#include <nrf24l01p.h>
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#include "core/ssp/ssp.h"
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#include "basic/xxtea.h"
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#define DEFAULT_SPEED R_RF_SETUP_DR_2M
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uint8_t _nrfresets=0;
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/*-----------------------------------------------------------------------*/
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/* Transmit a byte via SPI */
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/*-----------------------------------------------------------------------*/
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inline void xmit_spi(uint8_t dat) {
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sspSend(0, (uint8_t*) &dat, 1);
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}
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inline void rcv_spi(uint8_t *dat) {
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sspReceive(0, dat, 1);
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}
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#define CS_LOW() gpioSetValue(RB_SPI_NRF_CS, 0)
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#define CS_HIGH() gpioSetValue(RB_SPI_NRF_CS, 1)
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#define CE_LOW() gpioSetValue(RB_NRF_CE, 0)
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#define CE_HIGH() gpioSetValue(RB_NRF_CE, 1)
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void nrf_cmd(uint8_t cmd){
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CS_LOW();
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xmit_spi(cmd);
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CS_HIGH();
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};
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uint8_t nrf_cmd_status(uint8_t cmd){
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CS_LOW();
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sspSendReceive(0, &cmd, 1);
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CS_HIGH();
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return cmd;
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};
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void nrf_cmd_rw_long(uint8_t* data, int len){
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CS_LOW();
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sspSendReceive(0,data,len);
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CS_HIGH();
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};
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void nrf_write_reg(const uint8_t reg, const uint8_t val){
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CS_LOW();
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xmit_spi(C_W_REGISTER | reg);
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xmit_spi(val);
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CS_HIGH();
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};
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uint8_t nrf_read_reg(const uint8_t reg){
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uint8_t val;
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CS_LOW();
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xmit_spi(C_R_REGISTER | reg);
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rcv_spi(&val);
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CS_HIGH();
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return val;
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};
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void nrf_read_long(const uint8_t cmd, int len, uint8_t* data){
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CS_LOW();
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xmit_spi(cmd);
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for(int i=0;i<len;i++)
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data[i] = 0x00;
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sspSendReceive(0,data,len);
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CS_HIGH();
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};
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void nrf_read_pkt(int len, uint8_t* data){
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CS_LOW();
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xmit_spi(C_R_RX_PAYLOAD);
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sspReceive(0,data,len);
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CS_HIGH();
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};
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void nrf_read_pkt_crc(int len, uint8_t* data, uint8_t* crc){
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CS_LOW();
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xmit_spi(C_R_RX_PAYLOAD);
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sspReceive(0,data,len);
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sspReceive(0,crc,2);
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CS_HIGH();
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};
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void nrf_write_long(const uint8_t cmd, int len, const uint8_t* data){
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CS_LOW();
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xmit_spi(cmd);
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sspSend(0,data,len);
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CS_HIGH();
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};
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#define nrf_write_reg_long(reg, len, data) \
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nrf_write_long(C_W_REGISTER|(reg), len, data)
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// High-Level:
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void nrf_rcv_pkt_start(void){
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nrf_write_reg(R_CONFIG,
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R_CONFIG_PRIM_RX| // Receive mode
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R_CONFIG_PWR_UP| // Power on
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R_CONFIG_EN_CRC // CRC on, single byte
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);
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nrf_cmd(C_FLUSH_RX);
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nrf_write_reg(R_STATUS,0);
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CE_HIGH();
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};
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int nrf_rcv_pkt_poll(int maxsize, uint8_t * pkt){
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uint8_t len;
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uint8_t status=0;
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for(int i=0;i<maxsize;i++) pkt[i] = 0x00; // Sanity: clear packet buffer
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status =nrf_cmd_status(C_NOP);
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if((status & R_STATUS_RX_P_NO) == R_STATUS_RX_FIFO_EMPTY){
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if( (status & R_STATUS_RX_DR) == R_STATUS_RX_DR){
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#ifdef USB_CDC
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puts("FIFO empty, but RX?\r\n");
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#endif
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nrf_write_reg(R_STATUS,R_STATUS_RX_DR);
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};
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return 0;
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};
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nrf_read_long(C_R_RX_PL_WID,1,&len);
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nrf_write_reg(R_STATUS,R_STATUS_RX_DR);
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if(len>32 || len==0){
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return -2; // no packet error
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};
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if(len>maxsize){
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return -1; // packet too large
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};
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nrf_read_pkt(len,pkt);
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return len;
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};
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int nrf_rcv_pkt_poll_dec(int maxsize, uint8_t * pkt, uint32_t const key[4]){
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int len;
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uint16_t cmpcrc;
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len=nrf_rcv_pkt_poll(maxsize,pkt);
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if(len <=0)
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return len;
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// if(key==NULL) return len;
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if(key!=NULL)
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xxtea_decode_words((uint32_t*)pkt,len/4,key);
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cmpcrc=crc16(pkt,len-2);
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if(cmpcrc != (pkt[len-2] <<8 | pkt[len-1])) {
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return -3; // CRC failed
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};
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return len;
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};
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void nrf_rcv_pkt_end(void){
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CE_LOW();
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nrf_cmd(C_FLUSH_RX);
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nrf_write_reg(R_STATUS,R_STATUS_RX_DR);
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};
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// High-Level:
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int nrf_rcv_pkt_time_encr(int maxtime, int maxsize, uint8_t * pkt, uint32_t const key[4]){
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uint8_t len;
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uint8_t status=0;
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uint16_t cmpcrc;
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nrf_write_reg(R_CONFIG,
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R_CONFIG_PRIM_RX| // Receive mode
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R_CONFIG_PWR_UP| // Power on
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R_CONFIG_EN_CRC // CRC on, single byte
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);
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nrf_cmd(C_FLUSH_RX);
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nrf_write_reg(R_STATUS,0);
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CE_HIGH();
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for(int i=0;i<maxsize;i++) pkt[i] = 0x00; // Sanity: clear packet buffer
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#define LOOPY 10
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for (;maxtime >= LOOPY;maxtime-=LOOPY){
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delayms(LOOPY);
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status =nrf_cmd_status(C_NOP);
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if( (status & R_STATUS_RX_DR) == R_STATUS_RX_DR){
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if( (status & R_STATUS_RX_P_NO) == R_STATUS_RX_FIFO_EMPTY){
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nrf_cmd(C_FLUSH_RX);
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delayms(1);
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nrf_write_reg(R_STATUS,0);
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continue;
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}else{ // Get/Check packet...
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nrf_read_long(C_R_RX_PL_WID,1,&len);
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if(len>32 || len==0){
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continue;
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return -2; // no packet error
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};
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if(len>maxsize){
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continue;
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return -1; // packet too large
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};
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nrf_read_pkt(len,pkt);
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if(key != NULL)
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xxtea_decode_words((uint32_t*)pkt,len/4,key);
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cmpcrc=crc16(pkt,len-2);
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if(cmpcrc != (pkt[len-2] <<8 | pkt[len-1])) {
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continue;
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return -3; // CRC failed
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};
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break;
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};
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};
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};
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CE_LOW();
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CS_HIGH();
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if(maxtime<LOOPY)
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return 0; // timeout
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return len;
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};
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char nrf_snd_pkt_crc_encr(int size, uint8_t * pkt, uint32_t const key[4]){
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if(size > MAX_PKT)
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size=MAX_PKT;
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nrf_write_reg(R_CONFIG,
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R_CONFIG_PWR_UP| // Power on
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R_CONFIG_EN_CRC // CRC on, single byte
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);
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// nrf_write_long(C_W_TX_PAYLOAD,size,pkt);
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uint16_t crc=crc16(pkt,size-2);
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pkt[size-2]=(crc >>8) & 0xff;
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pkt[size-1]=crc & 0xff;
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if(key !=NULL)
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xxtea_encode_words((uint32_t*)pkt,size/4,key);
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CS_LOW();
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xmit_spi(C_W_TX_PAYLOAD);
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sspSend(0,pkt,size);
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CS_HIGH();
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CE_HIGH();
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delayms(1); // Send it. (only needs >10ys, i think)
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CE_LOW();
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return nrf_cmd_status(C_NOP);
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};
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void nrf_set_rx_mac(int pipe, int rxlen, int maclen, const uint8_t * mac){
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#ifdef SAFE
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assert(maclen>=1 || maclen<=5);
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assert(rxlen>=1 || rxlen<=32);
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assert(pipe>=0 || pipe<=5);
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assert(mac!=NULL);
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if(pipe>1)
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assert(maclen==1);
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#endif
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nrf_write_reg(R_RX_PW_P0+pipe,rxlen);
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nrf_write_reg_long(R_RX_ADDR_P0+pipe,maclen,mac);
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nrf_write_reg(R_EN_RXADDR,
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nrf_read_reg(R_EN_RXADDR) | (1<<pipe)
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);
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};
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void nrf_set_tx_mac(int maclen, const uint8_t * mac){
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#ifdef SAFE
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assert(maclen>=1 || maclen<=5);
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assert(mac!=NULL);
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#endif
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nrf_write_reg_long(R_TX_ADDR,maclen,mac);
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};
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void nrf_disable_pipe(int pipe){
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#ifdef SAFE
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assert(pipe>=0 || pipe<=5);
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#endif
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nrf_write_reg(R_EN_RXADDR,
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nrf_read_reg(R_EN_RXADDR) & ~(1<<pipe)
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);
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};
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void nrf_set_channel(int channel){
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#ifdef SAFE
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assert(channel &~R_RF_CH_BITS ==0);
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#endif
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nrf_write_reg(R_RF_CH, channel);
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};
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void nrf_config_set(nrfconfig config){
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nrf_write_reg(R_SETUP_AW,R_SETUP_AW_5);
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nrf_set_channel(config->channel);
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for(int i=0;i<config->nrmacs;i++){
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nrf_write_reg(R_RX_PW_P0+i,config->maclen[i]);
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if(i==0){
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nrf_write_reg_long(R_RX_ADDR_P0,5,config->mac0);
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}else if(i==1){
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nrf_write_reg_long(R_RX_ADDR_P1,5,config->mac1);
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}else if(i>1){
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nrf_write_reg_long(R_RX_ADDR_P0+i,1,config->mac2345+i-2);
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};
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};
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nrf_write_reg_long(R_TX_ADDR,5,config->txmac);
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nrf_write_reg(R_EN_RXADDR,(1<<config->nrmacs)-1);
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};
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void nrf_config_get(nrfconfig config){
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// nrf_write_reg(R_SETUP_AW,R_SETUP_AW_5);
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config->channel=nrf_read_reg(R_RF_CH);
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config->nrmacs=nrf_read_reg(R_EN_RXADDR);
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if(config->nrmacs & R_EN_RXADDR_ERX_P5 )
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config->nrmacs=6;
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else if(config->nrmacs & R_EN_RXADDR_ERX_P4 )
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config->nrmacs=5;
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else if(config->nrmacs & R_EN_RXADDR_ERX_P3 )
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config->nrmacs=4;
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else if(config->nrmacs & R_EN_RXADDR_ERX_P2 )
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config->nrmacs=3;
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else if(config->nrmacs & R_EN_RXADDR_ERX_P1 )
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config->nrmacs=2;
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else
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config->nrmacs=1;
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// config->nrmacs=6;
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for(int i=0;i<config->nrmacs;i++){
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config->maclen[i]=nrf_read_reg(R_RX_PW_P0+i);
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if(i==0){
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nrf_read_long(R_RX_ADDR_P0,5,config->mac0);
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}else if(i==1){
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nrf_read_long(R_RX_ADDR_P1,5,config->mac1);
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}else if(i>1){
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nrf_read_long(R_RX_ADDR_P0+i,1,config->mac2345+i-2);
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};
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};
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nrf_read_long(R_TX_ADDR,5,config->txmac);
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};
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void nrf_set_strength(unsigned char strength){
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if(strength>3)
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strength=3;
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nrf_write_reg(R_RF_SETUP,DEFAULT_SPEED|(strength<<1));
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};
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void nrf_init() {
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// Enable SPI correctly
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sspInit(0, sspClockPolarity_Low, sspClockPhase_RisingEdge);
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// Enable CS & CE pins
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gpioSetDir(RB_SPI_NRF_CS, gpioDirection_Output);
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gpioSetPullup(&RB_SPI_NRF_CS_IO, gpioPullupMode_Inactive);
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gpioSetDir(RB_NRF_CE, gpioDirection_Output);
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gpioSetPullup(&RB_NRF_CE_IO, gpioPullupMode_PullUp);
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CE_LOW();
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// Setup for nrf24l01+
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// power up takes 1.5ms - 3.5ms (depending on crystal)
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CS_LOW();
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nrf_write_reg(R_CONFIG,
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R_CONFIG_PRIM_RX| // Receive mode
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R_CONFIG_PWR_UP| // Power on
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R_CONFIG_EN_CRC // CRC on, single byte
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);
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nrf_write_reg(R_EN_AA, 0); // Disable Enhanced ShockBurst;
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// Set speed / strength
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nrf_write_reg(R_RF_SETUP,DEFAULT_SPEED|R_RF_SETUP_RF_PWR_3);
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// Clear MAX_RT, just in case.
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nrf_write_reg(R_STATUS,R_STATUS_MAX_RT);
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};
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void nrf_off() {
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nrf_write_reg(R_CONFIG,
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R_CONFIG_MASK_RX_DR|
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R_CONFIG_MASK_TX_DS|
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R_CONFIG_MASK_MAX_RT
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); // Most important: no R_CONFIG_PWR_UP
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};
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void nrf_startCW() {
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// Enable SPI correctly
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sspInit(0, sspClockPolarity_Low, sspClockPhase_RisingEdge);
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// Enable CS & CE pins
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gpioSetDir(RB_SPI_NRF_CS, gpioDirection_Output);
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gpioSetPullup(&RB_SPI_NRF_CS_IO, gpioPullupMode_Inactive);
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gpioSetDir(RB_NRF_CE, gpioDirection_Output);
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gpioSetPullup(&RB_NRF_CE_IO, gpioPullupMode_PullUp);
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CE_LOW();
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// Setup for nrf24l01+
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// power up takes 1.5ms - 3.5ms (depending on crystal)
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CS_LOW();
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nrf_write_reg(R_CONFIG, R_CONFIG_PWR_UP);
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delayms(2);
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nrf_write_reg(R_RF_SETUP, R_RF_SETUP_CONT_WAVE |
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R_RF_SETUP_PLL_LOCK |
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R_RF_SETUP_RF_PWR_3);
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nrf_write_reg(R_RF_CH, 81);
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CE_HIGH();
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}
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void nrf_check_reset(void){
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if(nrf_cmd_status(C_NOP) & R_STATUS_MAX_RT){
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_nrfresets++;
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nrf_init();
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};
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};
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