diff --git a/firmware/funk/nrf24l01p.c b/firmware/funk/nrf24l01p.c
index 0cb2422..cb89640 100644
--- a/firmware/funk/nrf24l01p.c
+++ b/firmware/funk/nrf24l01p.c
@@ -404,6 +404,29 @@ void nrf_off() {
             ); // Most important: no R_CONFIG_PWR_UP
 };
 
+void nrf_startCW() {
+    // Enable SPI correctly
+    sspInit(0, sspClockPolarity_Low, sspClockPhase_RisingEdge);
+
+    // Enable CS & CE pins
+    gpioSetDir(RB_SPI_NRF_CS, gpioDirection_Output);
+    gpioSetPullup(&RB_SPI_NRF_CS_IO, gpioPullupMode_Inactive);
+    gpioSetDir(RB_NRF_CE, gpioDirection_Output);
+    gpioSetPullup(&RB_NRF_CE_IO, gpioPullupMode_PullUp);
+    CE_LOW();
+
+    // Setup for nrf24l01+
+    // power up takes 1.5ms - 3.5ms (depending on crystal)
+    CS_LOW();
+
+    nrf_write_reg(R_CONFIG, R_CONFIG_PWR_UP);
+    delayms(2);
+    nrf_write_reg(R_RF_SETUP, R_RF_SETUP_CONT_WAVE |
+                              R_RF_SETUP_PLL_LOCK |
+                              R_RF_SETUP_RF_PWR_3);
+    nrf_write_reg(R_RF_CH, 81);
+    CE_HIGH();
+}
 
 void nrf_check_reset(void){
     if(nrf_cmd_status(C_NOP) & R_STATUS_MAX_RT){
diff --git a/firmware/funk/nrf24l01p.h b/firmware/funk/nrf24l01p.h
index 9b3d745..1f2121a 100644
--- a/firmware/funk/nrf24l01p.h
+++ b/firmware/funk/nrf24l01p.h
@@ -85,7 +85,7 @@
 #define R_RF_CH_BITS             0x7f
 
 //RF_SETUP register definitions
-#define R_RF_CONT_WAVE           0x80
+#define R_RF_SETUP_CONT_WAVE     0x80
 #define R_RF_SETUP_RF_DR_LOW     0x20
 #define R_RF_SETUP_PLL_LOCK      0x10
 #define R_RF_SETUP_RF_DR_HIGH    0x08
@@ -139,6 +139,7 @@ char nrf_snd_pkt_crc_encr(int size, uint8_t * pkt, uint32_t const k[4]);
 
 void nrf_init() ;
 void nrf_off() ;
+void nrf_startCW();
 
 void nrf_cmd(uint8_t cmd);
 uint8_t nrf_cmd_status(uint8_t cmd);