420 lines
14 KiB
C
420 lines
14 KiB
C
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/**************************************************************************/
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/*!
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@file pmu.c
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@author K. Townsend (microBuilder.eu)
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@date 22 March 2010
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@version 0.10
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@section DESCRIPTION
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Controls the power management features of the LPC1343, allowing you
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to enter sleep/deep-sleep or deep power-down mode.
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For examples of how to enter either mode, see the comments for the
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functions pmuSleep(), pmuDeepSleep() and pmuPowerDown().
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2010, microBuilder SARL
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**************************************************************************/
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#include "core/gpio/gpio.h"
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#include "core/cpu/cpu.h"
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#include "core/timer32/timer32.h"
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#include "pmu.h"
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#ifdef CFG_CHIBI
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#include "drivers/chibi/chb_drvr.h"
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#endif
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#define PMU_WDTCLOCKSPEED_HZ 7812
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void pmuSetupHW(void);
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void pmuRestoreHW(void);
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/**************************************************************************/
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/*!
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Wakeup interrupt handler
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*/
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/**************************************************************************/
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void WAKEUP_IRQHandler(void)
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{
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uint32_t regVal;
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// Reconfigure system clock/PLL
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cpuPllSetup(CPU_MULTIPLIER_6);
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// Clear match bit on timer
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TMR_TMR32B0EMR = 0;
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// Clear pending bits
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SCB_STARTRSRP0CLR = SCB_STARTRSRP0CLR_MASK;
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// Clear SLEEPDEEP bit
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SCB_SCR &= ~SCB_SCR_SLEEPDEEP;
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// Disable the deep sleep timer
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TMR_TMR32B0TCR = TMR_TMR32B0TCR_COUNTERENABLE_DISABLED;
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/* This handler takes care of all the port pins if they
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are configured as wakeup source. */
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regVal = SCB_STARTSRP0;
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if (regVal != 0)
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{
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SCB_STARTRSRP0CLR = regVal;
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}
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// Reconfigure CT32B0
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timer32Init(0, TIMER32_DEFAULTINTERVAL);
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timer32Enable(0);
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// Perform peripheral specific and custom wakeup tasks
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pmuRestoreHW();
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/* See tracker for bug report. */
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__asm volatile ("NOP");
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return;
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}
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/**************************************************************************/
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/*!
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Setup the clock for the watchdog timer. The default is 7.8125kHz.
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*/
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/**************************************************************************/
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static void pmuWDTClockInit (void)
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{
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/* Enable WDT clock */
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SCB_PDRUNCFG &= ~(SCB_PDRUNCFG_WDTOSC);
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/* Configure watchdog clock */
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/* Freq. = 0.5MHz, div = 64: WDT_OSC = 7.8125kHz */
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SCB_WDTOSCCTRL = SCB_WDTOSCCTRL_FREQSEL_0_5MHZ |
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SCB_WDTOSCCTRL_DIVSEL_DIV64;
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// Switch main clock to WDT output
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SCB_MAINCLKSEL = SCB_MAINCLKSEL_SOURCE_WDTOSC;
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SCB_MAINCLKUEN = SCB_MAINCLKUEN_UPDATE; // Update clock source
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SCB_MAINCLKUEN = SCB_MAINCLKUEN_DISABLE; // Toggle update register once
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SCB_MAINCLKUEN = SCB_MAINCLKUEN_UPDATE;
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// Wait until the clock is updated
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while (!(SCB_MAINCLKUEN & SCB_MAINCLKUEN_UPDATE));
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}
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/**************************************************************************/
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/*!
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@brief Initialises the power management unit
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*/
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/**************************************************************************/
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void pmuInit( void )
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{
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/* Enable all clocks, even those turned off at power up. */
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SCB_PDRUNCFG &= ~(SCB_PDRUNCFG_WDTOSC_MASK |
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SCB_PDRUNCFG_SYSOSC_MASK |
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SCB_PDRUNCFG_ADC_MASK);
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return;
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}
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/**************************************************************************/
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/*!
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@brief Puts select peripherals in sleep mode.
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This function will put the device into sleep mode. Most gpio pins
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can be used to wake the device up, but the pins must first be
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configured for this in pmuInit.
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@section Example
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@code
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// Configure wakeup sources before going into sleep/deep-sleep.
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// By default, pin 0.1 is configured as wakeup source (falling edge)
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pmuInit();
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// Enter sleep mode
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pmuSleep();
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@endcode
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*/
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/**************************************************************************/
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void pmuSleep()
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{
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SCB_PDAWAKECFG = SCB_PDRUNCFG;
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__asm volatile ("WFI");
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return;
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}
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/**************************************************************************/
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/*!
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@brief Turns off select peripherals and puts the device in deep-sleep
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mode.
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The device can be configured to wakeup from deep-sleep mode after a
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specified delay by supplying a non-zero value to the wakeupSeconds
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parameter. This will configure CT32B0 to toggle pin 0.1 (CT32B0_MAT2)
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after x seconds, waking the device up. The timer will be configured
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to run off the WDT OSC while in deep-sleep mode, meaning that WDTOSC
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should not be powered off (using the sleepCtrl parameter) when a
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wakeup delay is specified.
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The sleepCtrl parameter is used to indicate which peripherals should
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be put in sleep mode (see the SCB_PDSLEEPCFG register for details).
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@param[in] sleepCtrl
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The bits to set in the SCB_PDSLEEPCFG register. This
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controls which peripherals will be put in sleep mode.
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@param[in] wakeupSeconds
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The number of seconds to wait until the device will
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wakeup. If you do not wish to wakeup after a specific
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delay, enter a value of 0.
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@code
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uint32_t pmuRegVal;
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// Initialise power management unit
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pmuInit();
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// Put peripherals into sleep mode
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pmuRegVal = SCB_PDSLEEPCFG_IRCOUT_PD |
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SCB_PDSLEEPCFG_IRC_PD |
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SCB_PDSLEEPCFG_FLASH_PD |
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SCB_PDSLEEPCFG_USBPLL_PD |
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SCB_PDSLEEPCFG_SYSPLL_PD |
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SCB_PDSLEEPCFG_SYSOSC_PD |
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SCB_PDSLEEPCFG_ADC_PD |
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SCB_PDSLEEPCFG_BOD_PD;
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// Enter deep sleep mode (wakeup after 5 seconds)
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// By default, pin 0.1 is configured as wakeup source
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pmuDeepSleep(pmuRegVal, 5);
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@endcode
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*/
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/**************************************************************************/
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void pmuDeepSleep(uint32_t sleepCtrl, uint32_t wakeupSeconds)
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{
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// Setup the board for deep sleep mode, shutting down certain
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// peripherals and remapping pins for lower power
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pmuSetupHW();
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SCB_PDAWAKECFG = SCB_PDRUNCFG;
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sleepCtrl |= (1 << 9) | (1 << 11);
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SCB_PDSLEEPCFG = sleepCtrl;
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SCB_SCR |= SCB_SCR_SLEEPDEEP;
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/* Configure system to run from WDT and set TMR32B0 for wakeup */
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if (wakeupSeconds > 0)
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{
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// Make sure WDTOSC isn't disabled in PDSLEEPCFG
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SCB_PDSLEEPCFG &= ~(SCB_PDSLEEPCFG_WDTOSC_PD);
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// Disable 32-bit timer 0 if currently in use
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TMR_TMR32B0TCR = TMR_TMR32B0TCR_COUNTERENABLE_DISABLED;
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// Disable internal pullup on 0.1
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gpioSetPullup(&IOCON_PIO0_1, gpioPullupMode_Inactive);
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/* Enable the clock for CT32B0 */
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SCB_SYSAHBCLKCTRL |= (SCB_SYSAHBCLKCTRL_CT32B0);
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/* Configure 0.1 as Timer0_32 MAT2 */
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IOCON_PIO0_1 &= ~IOCON_PIO0_1_FUNC_MASK;
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IOCON_PIO0_1 |= IOCON_PIO0_1_FUNC_CT32B0_MAT2;
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/* Set appropriate timer delay */
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TMR_TMR32B0MR0 = PMU_WDTCLOCKSPEED_HZ * wakeupSeconds;
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/* Configure match control register to raise an interrupt and reset on MR0 */
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TMR_TMR32B0MCR |= (TMR_TMR32B0MCR_MR0_INT_ENABLED | TMR_TMR32B0MCR_MR0_RESET_ENABLED);
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/* Configure external match register to set 0.1 high on match */
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TMR_TMR32B0EMR &= ~(0xFF<<4); // Clear EMR config bits
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TMR_TMR32B0EMR |= TMR_TMR32B0EMR_EMC2_HIGH; // Set MAT2 (0.1) high on match
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/* Enable wakeup interrupts (any I/O pin can be used as a wakeup source) */
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//NVIC_EnableIRQ(WAKEUP0_IRQn); // P0.0
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NVIC_EnableIRQ(WAKEUP1_IRQn); // P0.1 (CT32B0_MAT2)
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//NVIC_EnableIRQ(WAKEUP2_IRQn); // P0.2
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//NVIC_EnableIRQ(WAKEUP3_IRQn); // P0.3
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//NVIC_EnableIRQ(WAKEUP4_IRQn); // P0.4
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//NVIC_EnableIRQ(WAKEUP5_IRQn); // P0.5
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//NVIC_EnableIRQ(WAKEUP6_IRQn); // P0.6
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//NVIC_EnableIRQ(WAKEUP7_IRQn); // P0.7
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//NVIC_EnableIRQ(WAKEUP8_IRQn); // P0.8
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//NVIC_EnableIRQ(WAKEUP9_IRQn); // P0.9
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//NVIC_EnableIRQ(WAKEUP10_IRQn); // P0.10
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//NVIC_EnableIRQ(WAKEUP11_IRQn); // P0.11
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//NVIC_EnableIRQ(WAKEUP12_IRQn); // P1.0
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//NVIC_EnableIRQ(WAKEUP13_IRQn); // P1.1
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//NVIC_EnableIRQ(WAKEUP14_IRQn); // P1.2
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//NVIC_EnableIRQ(WAKEUP15_IRQn); // P1.3
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//NVIC_EnableIRQ(WAKEUP16_IRQn); // P1.4
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//NVIC_EnableIRQ(WAKEUP17_IRQn); // P1.5
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//NVIC_EnableIRQ(WAKEUP18_IRQn); // P1.6
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//NVIC_EnableIRQ(WAKEUP19_IRQn); // P1.7
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//NVIC_EnableIRQ(WAKEUP20_IRQn); // P1.8
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//NVIC_EnableIRQ(WAKEUP21_IRQn); // P1.9
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//NVIC_EnableIRQ(WAKEUP22_IRQn); // P1.10
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//NVIC_EnableIRQ(WAKEUP23_IRQn); // P1.11
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//NVIC_EnableIRQ(WAKEUP24_IRQn); // P2.0
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//NVIC_EnableIRQ(WAKEUP25_IRQn); // P2.1
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//NVIC_EnableIRQ(WAKEUP26_IRQn); // P2.2
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//NVIC_EnableIRQ(WAKEUP27_IRQn); // P2.3
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//NVIC_EnableIRQ(WAKEUP28_IRQn); // P2.4
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//NVIC_EnableIRQ(WAKEUP29_IRQn); // P2.5
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//NVIC_EnableIRQ(WAKEUP30_IRQn); // P2.6
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//NVIC_EnableIRQ(WAKEUP31_IRQn); // P2.7
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//NVIC_EnableIRQ(WAKEUP32_IRQn); // P2.8
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//NVIC_EnableIRQ(WAKEUP33_IRQn); // P2.9
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//NVIC_EnableIRQ(WAKEUP34_IRQn); // P2.10
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//NVIC_EnableIRQ(WAKEUP35_IRQn); // P2.11
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//NVIC_EnableIRQ(WAKEUP36_IRQn); // P3.0
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//NVIC_EnableIRQ(WAKEUP37_IRQn); // P3.1
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//NVIC_EnableIRQ(WAKEUP38_IRQn); // P3.2
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//NVIC_EnableIRQ(WAKEUP39_IRQn); // P3.3
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/* Use RISING EDGE for wakeup detection. */
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SCB_STARTAPRP0 |= SCB_STARTAPRP0_APRPIO0_1;
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/* Clear all wakeup sources */
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SCB_STARTRSRP0CLR = SCB_STARTRSRP0CLR_MASK;
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/* Enable Port 0.1 as wakeup source. */
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SCB_STARTERP0 |= SCB_STARTERP0_ERPIO0_1;
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// Reconfigure clock to run from WDTOSC
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pmuWDTClockInit();
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/* Start the timer */
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TMR_TMR32B0TCR = TMR_TMR32B0TCR_COUNTERENABLE_ENABLED;
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}
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__asm volatile ("WFI");
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return;
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}
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/**************************************************************************/
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/*!
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@brief Puts the device in deep power-down mode.
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This function will configure the PMU control register and enter
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deep power-down mode. Pre-determined values are stored in the four
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general-purpose registers (PMU_GPREG0..3), which can be used to persist
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any essential system settings while the device is in deep power-down
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mode, so long as 3.3V is still available.
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@warning The only way to wake a device up from deep power-down mode
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is to set a low-level on P1.4. If 3.3V power is lost, the
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values stored in the four general-purpose registers will
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also be lost.
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@section Example
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@code
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#include "core/cpu/cpu.h"
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#include "core/pmu/pmu.h"
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int main(void)
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{
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cpuInit();
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pmuInit();
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|
// Enter power-down mode
|
||
|
|
pmuPowerDown();
|
||
|
|
|
||
|
|
while(1)
|
||
|
|
{
|
||
|
|
// Device was woken up by WAKEUP pin
|
||
|
|
}
|
||
|
|
}
|
||
|
|
@endcode
|
||
|
|
*/
|
||
|
|
/**************************************************************************/
|
||
|
|
void pmuPowerDown( void )
|
||
|
|
{
|
||
|
|
uint32_t regVal;
|
||
|
|
|
||
|
|
// Make sure HW and external devices are in low power mode
|
||
|
|
pmuSetupHW();
|
||
|
|
|
||
|
|
if ( (PMU_PMUCTRL & ((0x1<<8) | (PMU_PMUCTRL_DPDFLAG))) != 0x0 )
|
||
|
|
{
|
||
|
|
/* Check sleep and deep power down bits. If sleep and/or
|
||
|
|
deep power down mode are entered, clear the PCON bits. */
|
||
|
|
regVal = PMU_PMUCTRL;
|
||
|
|
regVal |= ((0x1<<8) |
|
||
|
|
(PMU_PMUCTRL_DPDEN_SLEEP) |
|
||
|
|
(PMU_PMUCTRL_DPDFLAG));
|
||
|
|
PMU_PMUCTRL = regVal;
|
||
|
|
|
||
|
|
if ( (PMU_GPREG0 != 0x12345678)||(PMU_GPREG1 != 0x87654321)
|
||
|
|
||(PMU_GPREG2 != 0x56781234)||(PMU_GPREG3 != 0x43218765) )
|
||
|
|
{
|
||
|
|
while (1);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* If in neither sleep nor deep-sleep mode, enter deep power down mode. */
|
||
|
|
PMU_GPREG0 = 0x12345678;
|
||
|
|
PMU_GPREG1 = 0x87654321;
|
||
|
|
PMU_GPREG2 = 0x56781234;
|
||
|
|
PMU_GPREG3 = 0x43218765;
|
||
|
|
SCB_SCR |= SCB_SCR_SLEEPDEEP;
|
||
|
|
PMU_PMUCTRL = PMU_PMUCTRL_DPDEN_DEEPPOWERDOWN;
|
||
|
|
__asm volatile ("WFI");
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**************************************************************************/
|
||
|
|
/*!
|
||
|
|
@brief Configures parts and system peripherals to use lower power
|
||
|
|
before entering sleep mode
|
||
|
|
*/
|
||
|
|
/**************************************************************************/
|
||
|
|
void pmuSetupHW(void)
|
||
|
|
{
|
||
|
|
#ifdef CFG_CHIBI
|
||
|
|
chb_sleep(TRUE);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**************************************************************************/
|
||
|
|
/*!
|
||
|
|
@brief Restores parts and system peripherals to an appropriate
|
||
|
|
state after waking up from deep-sleep mode
|
||
|
|
*/
|
||
|
|
/**************************************************************************/
|
||
|
|
void pmuRestoreHW(void)
|
||
|
|
{
|
||
|
|
#ifdef CFG_CHIBI
|
||
|
|
// Wakeup Chibi/Transceiver
|
||
|
|
chb_sleep(FALSE);
|
||
|
|
#endif
|
||
|
|
}
|