216 lines
5.2 KiB
C
216 lines
5.2 KiB
C
#include "../config.h"
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#include "../makros.h"
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <avr/wdt.h>
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#include "borg_hw.h"
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/*
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// those macros get defined via menuconfig, now
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// 16 columns total directly controlled, therefore 2 ports
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#define COLPORT1 PORTC
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#define COLDDR1 DDRC
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#define COLPORT2 PORTA
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#define COLDDR2 DDRA
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// the other port controls the shift registers
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#define ROWPORT PORTD
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#define ROWDDR DDRD
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// both clock and reset are connected to each shift register
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// reset pin is negated
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#define PIN_MCLR PD4
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#define PIN_CLK PD6
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// these are the individual data input pins for the shift registers
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#define PIN_DATA PD7
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*/
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#define COLDDR1 DDR(COLPORT1)
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#define COLDDR2 DDR(COLPORT2)
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#define ROWDDR DDR(ROWPORT)
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#if defined(__AVR_ATmega164__) || \
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defined(__AVR_ATmega164P__) || \
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defined(__AVR_ATmega324__) || \
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defined(__AVR_ATmega324P__) || \
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defined(__AVR_ATmega644__) || \
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defined(__AVR_ATmega644P__) || \
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defined(__AVR_ATmega1284__) || \
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defined(__AVR_ATmega1284P__)
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# define TIMER0_OFF() TCCR0A = 0; TCCR0B = 0
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# define TIMER0_CTC_CS256() TCCR0A = _BV(WGM01); TCCR0B = _BV(CS02)
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# define TIMER0_RESET() TCNT0 = 0
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# define TIMER0_COMPARE(t) OCR0A = t
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# define TIMER0_INT_ENABLE() TIMSK0 = _BV(OCIE0A)
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# define TIMER0_ISR TIMER0_COMPA_vect
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#else // ATmega16/32
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# define TIMER0_OFF() TCCR0 = 0
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# define TIMER0_CTC_CS256() TCCR0 = _BV(WGM01) | _BV(CS02)
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# define TIMER0_RESET() TCNT0 = 0
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# define TIMER0_COMPARE(t) OCR0 = t
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# define TIMER0_INT_ENABLE() TIMSK = _BV(OCIE0)
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# define TIMER0_ISR TIMER0_COMP_vect
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#endif
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// buffer which holds the currently shown frame
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unsigned char pixmap[NUMPLANE][NUM_ROWS][LINEBYTES];
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// switch to next row
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static void nextrow(uint8_t row) {
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//reset states of preceding row
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COLPORT1 = 0;
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COLPORT2 = 0;
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// short delay loop, to ensure proper deactivation of the drivers
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unsigned char i;
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for (i = 0; i < 10; i++) {
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asm volatile("nop");
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}
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if (row == 0) {
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// row 0: initialize first shift register
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#ifndef INVERT_ROWS
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ROWPORT |= (1 << PIN_DATA);
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ROWPORT |= (1 << PIN_CLK);
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ROWPORT &= ~(1 << PIN_CLK);
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ROWPORT &= ~(1 << PIN_DATA);
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#else
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ROWPORT&= ~(1<<PIN_DATA);
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ROWPORT|= (1<<PIN_CLK);
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ROWPORT&= ~(1<<PIN_CLK);
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ROWPORT|= (1<<PIN_DATA);
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#endif
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} else {
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// remaining rows: just shift forward
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ROWPORT |= (1 << PIN_CLK);
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ROWPORT &= ~(1 << PIN_CLK);
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}
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// another delay loop, to ensure that the drivers are ready
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for (i = 0; i < 20; i++) {
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asm volatile("nop");
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}
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}
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// show a row
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static void rowshow(unsigned char row, unsigned char plane) {
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// depending on the currently drawn plane, display the row for a specific
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// amount of time
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#ifdef HIGH_CONTRAST
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static unsigned char const ocr_table[] = {2, 5, 22};
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#else
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static unsigned char const ocr_table[] = {3, 4, 22};
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#endif
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TIMER0_COMPARE(ocr_table[plane]);
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// output data of the current row to the column drivers
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uint8_t tmp, tmp1;
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#ifndef INTERLACED_ROWS
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tmp = pixmap[plane][row][0];
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tmp1 = pixmap[plane][row][1];
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#else
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row = (row>>1) + ((row & 0x01)?8:0 );
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tmp = pixmap[plane][row][0];
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tmp1 = pixmap[plane][row][1];
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#endif
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#ifdef REVERSE_COLS
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tmp = (tmp >> 4) | (tmp << 4);
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tmp = ((tmp & 0xcc) >> 2) | ((tmp & 0x33)<< 2); //0xcc = 11001100, 0x33 = 00110011
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tmp = ((tmp & 0xaa) >> 1) | ((tmp & 0x55)<< 1); //0xaa = 10101010, 0x55 = 1010101
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COLPORT2 = tmp;
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tmp = tmp1;
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tmp = (tmp >> 4) | (tmp << 4);
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tmp = ((tmp & 0xcc) >> 2) | ((tmp & 0x33) << 2); //0xcc = 11001100, 0x33 = 00110011
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tmp = ((tmp & 0xaa) >> 1) | ((tmp & 0x55) << 1); //0xaa = 10101010, 0x55 = 1010101
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COLPORT1 = tmp;
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#else
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#ifdef INTERLACED_COLS
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static uint8_t interlace_table[16] = {
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0x00, 0x01, 0x04, 0x05, 0x10, 0x11, 0x14, 0x15, 0x40, 0x41, 0x44, 0x45,
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0x50, 0x51, 0x54, 0x55
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};
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COLPORT1 = interlace_table[tmp&0x0f] | (interlace_table[tmp1&0x0f]<<1);
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tmp>>=4; tmp1>>=4;
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COLPORT2 = interlace_table[tmp] | (interlace_table[tmp1]<<1);
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#else
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COLPORT1 = tmp;
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COLPORT2 = tmp1;
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#endif
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#endif
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}
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// interrupt handler
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ISR(TIMER0_ISR) {
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static unsigned char plane = 0;
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static unsigned char row = 0;
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// increment both row and plane
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if (++plane == NUMPLANE) {
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plane = 0;
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if (++row == NUM_ROWS) {
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// reset watchdog
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wdt_reset();
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row = 0;
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}
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nextrow(row);
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}
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// output current row according to current plane
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rowshow(row, plane);
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}
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// disables timer, causing the watchdog to reset the MCU
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void timer0_off() {
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cli();
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COLPORT1 = 0;
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COLPORT2 = 0;
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ROWPORT = 0;
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TIMER0_OFF();
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sei();
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}
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// initialize timer which triggers the interrupt
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static void timer0_on() {
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TIMER0_CTC_CS256(); // CTC mode, prescaling conforms to clk/256
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TIMER0_RESET(); // set counter to 0
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TIMER0_COMPARE(20); // compare with this value first
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TIMER0_INT_ENABLE(); // enable Timer/Counter0 Output Compare Match (A) Int.
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}
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void borg_hw_init() {
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// switch column ports to output mode
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COLDDR1 = 0xFF;
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COLDDR2 = 0xFF;
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// switch pins of the row port to output mode
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ROWDDR = (1 << PIN_CLK) | (1 << PIN_DATA);
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// switch off all columns for now
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COLPORT1 = 0;
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COLPORT2 = 0;
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// reset shift registers for the rows
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ROWPORT = 0;
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timer0_on();
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// activate watchdog timer
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wdt_reset();
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wdt_enable(WDTO_15MS); // 15ms watchdog
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}
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