49 lines
1.3 KiB
Makefile
49 lines
1.3 KiB
Makefile
# How to build automatic dependencies
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# Don't include dependencies if $(no_deps) is set; the master makefile
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# does this for clean and other such targets that don't need
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# dependencies. That then avoids rebuilding dependencies.
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ifneq ($(no_deps),t)
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ifneq ($(MAKECMDGOALS),clean)
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ifneq ($(MAKECMDGOALS),mrproper)
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ifneq ($(MAKECMDGOALS),menuconfig)
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# For each .o file we need a .d file.
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-include $(subst .o,.d,$(filter %.o,$(OBJECTS)))
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-include $(subst .o,.d,$(filter %.o,$(OBJECTS_SIM)))
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endif
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endif
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endif
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endif
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# Here is how to build those dependency files
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define make-deps
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echo "checking dependencies for $<"
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if [ ! -d obj_avr ]; then mkdir obj_avr ; fi
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set -e; $(CC) $(CFLAGS) $(CPPFLAGS) -M -MM $< | \
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sed > $@.new -e 's;$(*F)\.o:;$@ obj_avr/$*.o obj_avr/$*.E $*.s:;' \
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-e 's% [^ ]*/gcc-lib/[^ ]*\.h%%g'
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if test -s $@.new; then mv -f $@.new $@; else rm -f $@.new; fi
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endef
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# Here is how to make .d files from .c files
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obj_avr/%.d: %.c ; @ $(make-deps)
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obj_avr/%.d: %.S ; @ $(make-deps)
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define make-deps-sim
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echo "checking dependencies for $<"
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if [ ! -d obj_sim ]; then mkdir obj_sim ; fi
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set -e; $(HOSTCC) $(SIM_CFLAGS) -M -MM $< | \
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sed > $@.new -e 's;$(*F)\.o:;$@ obj_sim/$*.o obj_sim/$*.E $*.s:;' \
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-e 's% [^ ]*/gcc-lib/[^ ]*\.h%%g'
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if test -s $@.new; then mv -f $@.new $@; else rm -f $@.new; fi
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endef
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obj_sim/%.d: %.c ; @ $(make-deps-sim)
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